5M1270ZF324C5N

Manufacturer Part Number5M1270ZF324C5N
DescriptionIC MAX V CPLD 1270 LE 324-FBGA
ManufacturerAltera Corporation
SeriesMAX® V
5M1270ZF324C5N datasheet
 

Specifications of 5M1270ZF324C5N

Programmable TypeIn System ProgrammableDelay Time Tpd(1) Max6.2ns
Voltage Supply - Internal1.71 V ~ 1.89 VNumber Of Logic Elements/blocks1270
Number Of Macrocells980Number Of Gates-
Number Of I /o271Operating Temperature0°C ~ 85°C
Mounting TypeSurface MountPackage / Case324-LBGA
Lead Free StatusVendor undefinedRohs StatusRoHS Compliant
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May 2011
MV51003-1.2
MV51003-1.2
This chapter covers the electrical and switching characteristics for MAX
Electrical characteristics include operating conditions and power consumptions. This
chapter also describes the timing model and specifications.
You must consider the recommended DC and switching conditions described in this
chapter to maintain the highest possible performance and reliability of the MAX V
devices.
This chapter contains the following sections:
“Operating Conditions” on page 3–1
“Power Consumption” on page 3–10
“Timing Model and Specifications” on page 3–10
Operating Conditions
Table 3–1
through
ratings, recommended operating conditions, DC electrical characteristics, and other
specifications for MAX V devices.
Absolute Maximum Ratings
Table 3–1
lists the absolute maximum ratings for the MAX V device family.
Table 3–1. Absolute Maximum Ratings for MAX V Devices
Symbol
Parameter
V
Internal supply voltage
CCINT
V
I/O supply voltage
CCIO
V
DC input voltage
I
I
DC output current, per pin
OUT
T
Storage temperature
STG
T
Ambient temperature
AMB
T
Junction temperature
J
Notes to
Table
3–1:
(1) For more information, refer to the
Operating Requirements for Altera Devices Data
(2) Conditions beyond those listed in
Table 3–1
ratings for extended periods of time may have adverse affects on the device.
(3) For more information about “under bias” conditions, refer to
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
MAX V Device Handbook
May 2011
3. DC and Switching Characteristics for
Table 3–15 on page 3–9
list information about absolute maximum
(Note
1),
(2)
Conditions
Minimum
With respect to ground
No bias
Under bias
(3)
TQFP and BGA packages
under bias
Sheet.
may cause permanent damage to a device. Additionally, device operation at the absolute maximum
Table
3–2.
MAX V Devices
®
V devices.
Maximum
Unit
–0.5
2.4
V
–0.5
4.6
V
–0.5
4.6
V
–25
25
mA
–65
150
°C
–65
135
°C
135
°C
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5M1270ZF324C5N Summary of contents

  • Page 1

    ... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...

  • Page 2

    ... Commercial range 0 Industrial range –40 Extended range (5) –40 Using MAX V Devices in Multi-Voltage Systems and V are powered. CCINT CCIO May 2011 Altera Corporation Operating Conditions Maximum Unit 1.89 V 3.60 V 2.625 V 1.89 V 1.575 V 1. CCIO 85 °C 100 ° ...

  • Page 3

    ... V (8) SCHMITT trigger input (9) V supply current CCINT I CCPOWERUP during power-up (10) Value of I/O pin pull-up R resistor during user PULLUP mode and ISP May 2011 Altera Corporation Block Minimum — — (Note 1) (Part Conditions Minimum = V max (2) –10 I CCIO max (2) – ...

  • Page 4

    ... Chapter 3: DC and Switching Characteristics for MAX V Devices (Note 1) (Part Conditions Minimum — — — — — — = 1.2, 1.5, 1.8, 2.5, or 3.3 V. CCIO time. CONFIG . CCIO Operating Conditions Typical Maximum Unit — 300 µA — — settings (3.3, 2.5, 1.8, 1.5, CCIO typical value is 300 mV SCHMITT May 2011 Altera Corporation ...

  • Page 5

    ... High-level output voltage OH V Low-level output voltage OL Note to Table 3–5: (1) This specification is supported across all the programmable drive strength settings available for this I/O standard, as shown in the MAX V Device Architecture chapter. May 2011 Altera Corporation (Note 1) MAX V Output Drive 0.0 ...

  • Page 6

    ... IOH = –2 mA (1) V – 0.45 CCIO IOL = 2 mA (1) — maximum of 4.0, as specified by the V IH Operating Conditions Maximum Unit 3.6 V 4.0 V 0.8 V — V 0.2 V Maximum Unit 2.625 V 4.0 V 0.7 V — V — V — V 0.2 V 0.4 V 0.7 V Maximum Unit 1.89 V 2.25 (2) V 0.35 × CCIO — V 0.45 V parameter I May 2011 Altera Corporation ...

  • Page 7

    ... Parameter V I/O supply voltage CCIO V Differential output voltage swing OD V Output offset voltage OS Note to Table 3–12: (1) Supports emulated LVDS output using a three-resistor network (LVDS_E_3R). May 2011 Altera Corporation Conditions Minimum — 1.425 — 0.65 × V CCIO — –0.3 IOH = –2 mA (1) 0.75 × V CCIO ...

  • Page 8

    ... Operating Conditions Typical Maximum Unit 2.5 2.625 V — 600 mV 1.25 1.375 V 2.5 V 3.3 V Unit Min Max Min Max 50 — 70 — µA –50 — –70 — µA — 300 — 500 µA — –300 — –500 µA May 2011 Altera Corporation ...

  • Page 9

    ... Not applicable to the T144 package of the 5M240Z device. (3) Only applicable to the T144 package of the 5M240Z device. (4) Not applicable to the F324 package of the 5M1270Z device. (5) Only applicable to the F324 package of the 5M1270Z device. May 2011 Altera Corporation Device Temperature Range Commercial and industrial ...

  • Page 10

    ... To Adjacent LE Register Delays Data-Out AN629: Understanding Timing in Altera Power Consumption PowerPlay Early PowerPlay Power Analysis chapter ® II software, a variety Output and Output Enable Data Delay t IODR t IOE Output Routing Output Delay Delay FASTIO I/O Pin ZX CPLDs. May 2011 Altera Corporation ...

  • Page 11

    ... LE 32-to-1 multiplexer — 16-bit XOR function — 16-bit decoder with — single address line May 2011 Altera Corporation Table 3–16 lists the status of the MAX V device timing models. Device 5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z Resources Used 5M40Z/ 5M80Z/ 5M160Z/ ...

  • Page 12

    ... Min Max — 742 — 914 — 192 — 236 309 — 381 — 309 — 381 — 271 — 333 — 0 — 0 — — 305 — 376 May 2011 Altera Corporation Unit MHz MHz MHz kHz Unit ...

  • Page 13

    ... Table 3–23 on page 3–15. (4) For more information about t delay adders associated with different I/O standards, drive strengths, and slew rates, refer to ZX page 3–14 and Table 3–21 on page 3–14. May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max 253 — ...

  • Page 14

    ... Max 6,012 — 5,743 ps 8,785 — 8,516 ps 6,012 — 5,743 ps 8,785 — 8,516 ps 10,072 — 9,803 ps 12,945 — 12,676 ps 21,185 — 20,916 ps 24,597 — 24,328 ps 34,517 — 34,248 ps 39,717 — 39,448 ps 55,800 — 55,531 ps 35 — May 2011 Altera Corporation ...

  • Page 15

    ... LVCMOS 7 mA — — 1.8-V LVTTL / LVCMOS 3 mA — — 1.5-V LVCMOS 2 mA — 1.2-V LVCMOS 3 mA — 3.3-V PCI 20 mA — May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min Max Min 0 — 0 — –69 — –69 — 0 — 0 — ...

  • Page 16

    ... May 2011 Altera Corporation µs ...

  • Page 17

    ... Maximum delay between the OSC_ENA rising edge t OSCS to the erase/program signal rising edge Minimum delay allowed from the t erase/program signal OSCH going low to OSC_ENA signal going low May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Min Max Min Max 0 — 0 — ...

  • Page 18

    ... Table 3–24. 9 Address Bits t AH ACLK t ADH 16 Data Bits t DCLK t DSS t DCO ADH 16 Data Bits t t DCLK DSS t DDH t DDS Timing Model and Specifications t DSH t DSH t t OSCH OSCS PPMX May 2011 Altera Corporation ...

  • Page 19

    ... For external I/O timing using standards other than LVTTL or for different drive strengths, use the I/O standard input and output delay adders in f For more information about each external timing parameters symbol, refer to AN629: Understanding Timing in Altera May 2011 Altera Corporation 9 Address Bits ACLK ...

  • Page 20

    ... May 2011 Altera Corporation C5, I5 Unit Max 14.0 ns 8.5 ns — ns — ns 8.6 ns — ps — ps — ns 118.3 MHz C5, I5 Unit Max 17.7 ns 8.5 ns — ...

  • Page 21

    ... The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. (2) Not applicable to the F324 package of the 5M1270Z device. May 2011 Altera Corporation (Note 1) C4 Condition ...

  • Page 22

    ... May 2011 Altera Corporation C5, I5 Unit Max 11.2 ns 5.9 ns — ns — ns 7.4 ns — ps — ps — ns 201.1 MHz C5, I5 Unit Max 11.2 ns 5.9 ns — ...

  • Page 23

    ... Table 3–33. External Timing Input Delay t I/O Standard Min Without Schmitt Trigger 3.3-V LVTTL With Schmitt Trigger May 2011 Altera Corporation Table 3–36 on page 3–25 list the adder delays associated with I/O timing parameters listed in SU Table 3–31. If you select an I/O standard other than 3.3-V LVTTL listed in Table 3– ...

  • Page 24

    ... May 2011 Altera Corporation Unit Unit ...

  • Page 25

    ... Table 3–36. IOE Programmable Delays for MAX V Devices Parameter Min Input Delay from Pin to Internal — Cells = 1 Input Delay from Pin to Internal — Cells = 0 May 2011 Altera Corporation Adders for Slow Slew Rate for MAX V Devices OD 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z C4 C5, I5 Max Min ...

  • Page 26

    ... MHz 200 MHz 150 MHz 120 MHz 304 MHz 5M40Z/ 5M80Z/ 5M160Z/ Unit 5M2210Z C4, C5, I5 304 MHz 304 MHz 304 MHz 304 MHz 200 MHz 200 MHz 150 MHz 120 MHz 304 MHz 304 MHz 200 MHz May 2011 Altera Corporation ...

  • Page 27

    ... ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through MAX the Quartus II timing analysis of the complete design. (2) For the input clock pin to achieve 304 Mbps, use I/O standard with V (3) This specification is based on external clean clock source. May 2011 Altera Corporation 5M40Z/ 5M80Z/ 5M160Z/ 5M240Z/ 5M570Z/5M1270Z/ Mode Min  ...

  • Page 28

    ... V and above. CCIO Timing Model and Specifications 5M2210Z Unit C4, C5, I5 Max 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 200 Mbps 55 % 0.2 UI 450 ps 450 ps May 2011 Altera Corporation ...

  • Page 29

    ... JTAG port valid output to high impedance JPXZ t Capture register setup time JSSU t Capture register hold time JSH t Update register clock to output JSCO t Update register high impedance to valid output JSZX May 2011 Altera Corporation t JCP t t JPSU JPH t JCL t JPZX JPCO t t JSSU ...

  • Page 30

    ... JPCO JPZX JPXZ Changes Updated Table 3–2, Table 3–15, Table 3–16, and Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40. Initial release. Document Revision History Min Max Unit — Table 3–33. May 2011 Altera Corporation ...