STM32F105V8 STMicroelectronics, STM32F105V8 Datasheet - Page 65

• Manufacturer Part Number: STM32F105V8
• Description: Mainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
• Manufacturer: STMicroelectronics

Specifications of STM32F105V8

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter
• 10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

STM32F105xx, STM32F107xx
I
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK,
SD for I
Table 43.
2
DuCy(SCK)
S - SPI interface characteristics
1/t
Symbol
t
t
t
w(SCKH)
t
w(SCKL)
t
t
su(NSS)
t
t
t
t
t
t
h(NSS)
t
r(SCK)
f(SCK)
t
f
su(MI)
t
v(MO)
h(MO)
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
c(SCK)
h(SI)
SCK
2
Section 5.3.12: I/O current injection characteristics
S).
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
Parameter
Doc ID 15274 Rev 6
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode (after enable edge)
Master mode (after enable edge)
Table
Conditions
9.
PCLK
PCLK
= 20 MHz
Table 43
= 36 MHz,
for more details on the
for SPI or in
Electrical characteristics
PCLKx
4 t
2 t
Min
30
32
10
PCLK
PCLK
50
4
5
5
5
frequency and V
Table 44
3*t
Max
18
70
60
34
18
PCLK
8
8
for I
65/104
MHz
Unit
ns
ns
%
2
S
DD