STM32F105V8 STMicroelectronics, STM32F105V8 Datasheet - Page 69

• Manufacturer Part Number: STM32F105V8
• Description: Mainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
• Manufacturer: STMicroelectronics

Specifications of STM32F105V8

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter
• 10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

STM32F105xx, STM32F107xx
Figure 28. I
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
Figure 29. I
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
byte.
SD transmit
SD receive
SD transmit
SD receive
WS output
WS input
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
2
2
S slave timing diagram (Philips protocol)
S master timing diagram (Philips protocol)
t v(WS)
t su(WS)
t w(CKH)
t w(CKH)
LSB receive
Doc ID 15274 Rev 6
LSB transmit
LSB transmit
LSB receive
t su(SD_MR)
t su(SD_SR)
t c(CK)
t c(CK)
(2)
(2)
(2)
(2)
MSB receive
DD
MSB receive
MSB transmit
MSB transmit
and 0.7 × V
t w(CKL)
t w(CKL)
t f(CK)
(1)
DD
(1)
t h(SD_MR)
.
t v(SD_MT)
t v(SD_ST)
t h(SD_SR)
Bitn receive
Bitn transmit
Bitn transmit
Bitn receive
Electrical characteristics
t r(CK)
LSB receive
t h(WS)
t h(WS)
t h(SD_ST)
LSB transmit
LSB receive
t h(SD_MT)
LSB transmit
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