STM32F105V8 STMicroelectronics, STM32F105V8 Datasheet - Page 97

• Manufacturer Part Number: STM32F105V8
• Description: Mainstream Connectivity line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
• Manufacturer: STMicroelectronics

Specifications of STM32F105V8

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter
• 10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

STM32F105xx, STM32F107xx
Table 63.
1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz.
Ethernet only
Ethernet + OTG
Ethernet + OTG
+ basic audio
Ethernet + OTG
+ Audio class
I
OTG only
OTG + basic
audio
OTG + Audio
class I
Audio class I
only
2
S
Application
(1)
(1)
2
S
(1)
2
S
PLL configurations
Table 64
Table
value in
14.7456
14.7456
14.7456
Crystal
(XT1)
MHz
25
25
25
8
8
63.
PREDIV2 PLL2MUL PLLSRC
give the I
NA
NA
/5
/5
/5
/4
/4
/4
PLL2OFF
PLL2OFF
PLL2ON
PLL2ON
PLL2ON
PLL2ON
PLL2ON
PLL2ON
DD
x12
x12
x12
x8
x8
x8
run mode values that correspond to the conditions specified in
PLL2
PLL2
PLL2
PLL2
PLL2
PLL2
XT1
XT1
Doc ID 15274 Rev 6
PREDIV1
/5
/5
/5
/4
/1
/1
/4
/4
PLLON x9
PLLON x9
PLLON x9
PLLON x9
PLLON x9
PLLMUL
PLLON
PLLON
PLLON
x6.5
x6.5
x6.5
prescaler
(PLLVCO
output)
USB
NA
NA
/3
/3
/3
/3
/3
/3
Application block diagrams
PLL3MUL
PLL3OFF
PLL3OFF
PLL3ON
PLL3ON
PLL3ON
PLL3ON
PLL3ON
PLL3ON
x10
x10
x10
x20
x20
x20
clock
input
PLL3
PLL3
PLL3
VCO
VCO
VCO
I2Sn
PLL
PLL
Out
Out
NA
NA
NA
out
MCO (main
PLL3 (RMII)
PLL3 (RMII)
PLL3 (RMII)
must use its
own crystal
ETH PHY
XT1 (MII)
XT1 (MII)
XT1 (MII)
output)
clock
NA
NA
NA
NA
NA
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