STM32F105VC STMicroelectronics, STM32F105VC Datasheet - Page 14

• Manufacturer Part Number: STM32F105VC
• Description: Mainstream Connectivity line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, CAN, USB 2.0 OTG
• Manufacturer: STMicroelectronics

Specifications of STM32F105VC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter
• 10/100 Ethernet Mac With Dedicated Dma And Sram (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

Description
2.3.6
2.3.7
2.3.8
14/104
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 20 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG
FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency,
the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum
frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed
frequency of the low speed APB domain is 36 MHz. Refer to
Ethernet solution on page
The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In order to achieve audio class performance, an audio crystal can be used. In this
case, the I
96 kHz with less than 0.5% accuracy error. Refer to
solution on page
To configure the PLLs, please refer to
configurations according to the application type.
Boot modes
At startup, boot pins are used to select one of three boot options:
●
●
●
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode
(DFU: device firmware upgrade). For remapped signals refer to
The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN
and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock
(HSE) is present.
For full details about the boot loader, please refer to AN2606.
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
2
S master clock can generate all standard sampling frequencies from 8 kHz to
96.
96.
Doc ID 15274 Rev 6
Table 63 on page
Figure 56: USB OTG FS + I2S (Audio)
97, which provides PLL
STM32F105xx, STM32F107xx
Figure 55: USB OTG FS +
Table 5: Pin
definitions.