STM32F103T8

Manufacturer Part NumberSTM32F103T8
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103T8 datasheet
 

Specifications of STM32F103T8

Conversion Range0 to 3.6 VPeripherals Supportedtimers, ADC, SPIs, I2Cs and USARTs
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STM32F103x8, STM32F103xB
Table 5.
Medium-density STM32F103xx pin definitions (continued)
Pins
C5
41
C4
57
91 32
B5
42
D3
58
92 33
A5
43
C3
59
93 34
D5
44
B4
60
94 35
B4
45
B3
61
95
-
A4
46
A3
62
96
-
D4
-
-
-
97
-
C4
-
-
-
98
-
E5
47
D4
63
99 36
F5
48
E4
64 100 1
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
Main
Pin name
function
(after reset)
PB5
I/O
PB5
PB6
I/O FT
PB6
PB7
I/O FT
PB7
BOOT0
I
BOOT0
PB8
I/O FT
PB8
PB9
I/O FT
PB9
PE0
I/O FT
PE0
PE1
I/O FT
PE1
V
S
V
SS_3
SS_3
V
S
V
DD_3
DD_3
Table 2 on page
10.
Doc ID 13587 Rev 13
Pinouts and pin description
(4)
Alternate functions
(3)
Default
Remap
TIM3_CH2 /
I2C1_SMBAl
SPI1_MOSI
(8)
I2C1_SCL
/
USART1_TX
(8)
TIM4_CH1
(8)
I2C1_SDA
/
USART1_RX
(8)
TIM4_CH2
I2C1_SCL /
(8)
TIM4_CH3
CANRX
I2C1_SDA/
(8)
TIM4_CH4
CANTX
TIM4_ETR
functionality is provided instead.
REF+
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