STM32F103RC STMicroelectronics, STM32F103RC Datasheet - Page 93

• Manufacturer Part Number: STM32F103RC
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103RC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F103xC, STM32F103xD, STM32F103xE
5.3.17
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
performance line I
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V
The I
characteristics
and SCL) .
Table 51.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
to achieve the fast mode I
mode maximum clock speed of 400 kHz.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be higher than 2 MHz to achieve standard mode I
DD
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
is disabled, but is still present.
I
2
C characteristics
for more details on the input/output alternate function characteristics (SDA
Table
2
C interface meets the requirements of the standard I
Parameter
10.
2
C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
Doc ID 14611 Rev 8
Standard mode I
PCLK1
Table
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
frequency and V
51. Refer also to
2
Table 51
C frequencies. It must be higher than 4 MHz
1000
Max
300
400
2
C
(1)
are derived from tests
20 + 0.1C
DD
Fast mode I
Section 5.3.14: I/O port
Electrical characteristics
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
supply voltage conditions
(4)
b
2
C communication
2
C
900
Max
300
300
400
(1)(2)
(3)
93/130
Unit
μs
μs
pF
µs
ns
µs