STM32F101C8 STMicroelectronics, STM32F101C8 Datasheet - Page 51

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STM32F101C8

Manufacturer Part Number
STM32F101C8
Description
Mainstream Access line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 36 MHz CPU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F101C8

Peripherals Supported
timers, ADC, SPIs, I2Cs and USARTs
Conversion Range
0 to 3.6 V
Systick Timer
24-bit downcounter
STM32F101x8, STM32F101xB
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in
defined in application note AN1709.
Table 29.
EMS characteristics
Symbol
Voltage limits to be applied on any I/O pin to
V
FESD
induce a functional disturbance
Fast transient voltage burst limits to be
V
applied through 100 pF on V
EFTB
to induce a functional disturbance
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table
29. They are based on the EMS levels and classes
Parameter
V
DD
f
HCLK
conforms to IEC 61000-4-2
V
DD
and V
pins
f
DD
SS
HCLK
conforms to IEC 61000-4-4
Doc ID 13586 Rev 14
Electrical characteristics
and
DD
Conditions
Level/Class
= 3.3 V, T
= +25 °C,
A
= 36 MHz
2B
= 3.3 V, T
= +25 °C,
A
= 36 MHz
4A
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