STM32F101VD STMicroelectronics, STM32F101VD Datasheet - Page 13

• Manufacturer Part Number: STM32F101VD
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 384 Kbytes Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101VD

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, DAC, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F101xC, STM32F101xD, STM32F101xE
Figure 2.
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
OSC32_OUT
OSC32_IN
OSC_OUT
36 MHz.
OSC_IN
MCO
Clock tree
4-16 MHz
32.768 kHz
Main
Clock Output
HSE OSC
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
PLLXTPRE
PLL
/2
/128
LSE
/2
LSI
RTCSEL[1:0]
/2
HSE
PLLCLK
SYSCLK
HSI
Doc ID 14610 Rev 8
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
36 MHz
to RTC
max
IWDGCLK
FLITFCLK
to Flash programming interface
Prescaler
/1, 2..512
AHB
/1, 2, 4, 8, 16
/1, 2, 4, 8, 16
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
Peripheral clock
enable
/8
Prescaler
Prescaler
36 MHz max
APB1
APB2
Clock
Enable (7 bits)
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
Legend:
else x2
36 MHz max
36 MHz max
Peripheral Clock
Prescaler
/2, 4, 6, 8
Peripheral Clock
Enable (18 bits)
Enable (11 bits)
ADC
Peripheral Clock
Enable (6 bits)
HCLK
to AHB bus, core,
memory and DMA
FCLK Cortex
free running clock
to Cortex System timer
FSMCCLK
to TIM2,3,4,5,6 and 7
ADCCLK
TIMXCLK
peripherals to APB2
PCLK1
to APB1
peripherals
PCLK2
to FSMC
Description
to ADC
ai15100
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