STM32F101VD STMicroelectronics, STM32F101VD Datasheet - Page 17

• Manufacturer Part Number: STM32F101VD
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 384 Kbytes Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101VD

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, DAC, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F101xC, STM32F101xD, STM32F101xE
2.3.11
2.3.12
2.3.13
2.3.14
Power supply schemes
●
●
●
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
than the V
message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to
Table 12: Embedded reset and power control block characteristics
V
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
This regulator is always enabled after reset. It is disabled in Standby mode.
Low-power modes
The STM32F101xC, STM32F101xD and STM32F101xE access line supports three low-
power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:
●
●
DD
POR/PDR
/V
V
Provided externally through V
V
RCs and PLL (minimum voltage to be applied to V
used). V
V
registers (through power switch) when V
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop modes.
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
DD
SSA
BAT
DDA
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
PVD
and V
power supply and compares it to the V
DDA
DDA
threshold. The interrupt service routine can then generate a warning
PVD
= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
and V
DD
.
/V
DD
DDA
SSA
is below a specified threshold, V
drops below the V
must be connected to V
Doc ID 14610 Rev 8
DD
pins.
DD
PVD
is not present.
PVD
threshold and/or when V
DD
threshold. An interrupt can be
DDA
and V
Figure 9: Power supply
POR/PDR
is 2.4 V when the ADC or DAC is
SS
, respectively.
, without the need for an
for the values of
DD
/V
DDA
Description
scheme.
is higher
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