STM32F101VD STMicroelectronics, STM32F101VD Datasheet - Page 30

• Manufacturer Part Number: STM32F101VD
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 384 Kbytes Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101VD

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, DAC, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

Pinouts and pin descriptions
Table 5.
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
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133
134
135
136
137
138
139
140
141
142
143
144
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual
Pins
55
56
57
58
59
60
61
62
63
64
-
-
100
89
90
91
92
93
94
95
96
97
98
99
High-density STM32F101xx pin definitions (continued)
Pin name
BOOT0
V
V
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
I/O FT
I/O FT
I/O
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I
Doc ID 14610 Rev 8
(after reset)
function
NJTRST
BOOT0
V
JTDO
V
Main
PB5
PB6
PB7
PB8
PB9
PE0
PE1
SS_3
DD_3
STM32F101xC, STM32F101xD, STM32F101xE
(3)
I2C1_SMBA/ SPI3_MOSI
I2C1_SCL/ TIM4_CH1
I2C1_SDA/FSMC_NADV
TIM4_CH3
TIM4_CH4
TIM4_ETR
TIM4_CH2
FSMC_NBL0
FSMC_NBL1
SPI3_MISO
SPI3_SCK
Default
Alternate functions
(7)
(7)
(7)
(7)
/
(7)
PB4 / TIM3_CH1
TIM2_CH2 /PB3
USART1_RX
TRACESWO
USART1_TX
TIM3_CH2 /
SPI1_MISO
SPI1_MOSI
SPI1_SCK
I2C1_SDA
I2C1_SCL
(4)
Remap