STM32F101VD STMicroelectronics, STM32F101VD Datasheet - Page 80

• Manufacturer Part Number: STM32F101VD
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 384 Kbytes Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101VD

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, DAC, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

Electrical characteristics
5.3.14
Table 46.
1. FT = Five-volt tolerant. In order to sustain a voltage higher than V
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
80/112
Symbol
V
R
R
C
V
V
I
disabled.
PMOS/NMOS contribution
lkg
hys
PU
PD
IH
IO
IL
Standard IO input low
level voltage
IO FT
voltage
Standard IO input high
level voltage
IO FT
voltage
Standard IO Schmitt
trigger voltage
hysteresis
IO FT Schmitt trigger
voltage hysteresis
Input leakage current
Weak pull-up equivalent
resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
in
(1)
(1)
Figure 41
Parameter
(5)
input low level
input high level
(2)
to the series resistance is minimum
and
(2)
(5)
(4)
Figure 42
V
V
V
DD
DD
Standard I/Os
SS
Conditions
V
V
> 2 V
≤
V
≤
I/O FT
IN
IN
IN
2 V
V
=
for 5 V tolerant I/Os.
=
= 5 V
IN
V
V
≤
DD
SS
Doc ID 14610 Rev 8
V
DD
(~10% order)
0.41*(V
0.42*(V
5% V
DD
STM32F101xC, STM32F101xD, STM32F101xE
DD
Figure 39
+0.3 the internal pull-up/pull-down resistors must be
DD
–0.3
–0.3
Min
200
30
30
-2 V)+1.3 V
Table
-2 V)+1 V
DD
.
(3)
Table 46
10. All I/Os are CMOS and TTL
and
Typ
Figure 40
40
40
5
are derived from tests
0.32*(V
0.28*(V
for standard I/Os, and
V
DD
DD
DD
Max
5.5
5.2
50
50
±1
-2V)+0.75 V
-2 V)+0.8 V
3
+0.3
Unit
mV
mV
µA
kΩ
kΩ
pF
V
V
V
V