STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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Revision history
Table 75.
Document revision history
Date
Revision
21-Jul-2009
24-Sep-2009
128/130
STM32F103xC, STM32F103xD, STM32F103xE
Figure 1: STM32F103xC, STM32F103xD and STM32F103xE
performance line block diagram
Note 5
updated and
Note 4
STM32F103xx pin
definitions.
V
and T
added to
RERINT
Coeff
voltage.
Table 16: Maximum current consumption in Sleep mode, code running
from Flash or RAM
modified.
f
min modified in
Table 21: High-speed external user clock
HSE_ext
characteristics.
C
and C
replaced by C in
L1
L2
characteristics
and
Table 24: LSE oscillator characteristics (fLSE =
32.768
kHz), notes modified and moved below the tables.
Note 1
modified below
Figure 22: Typical application with an 8 MHz
crystal.
Table 25: HSI oscillator characteristics
removed from
Table 27: Low-power mode wakeup
Jitter added to
Table 28: PLL
Figure 47: Recommended NRST pin protection
In
Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
timings: t
and t
6
h(BL_NOE)
h(A_NOE)
In
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings: t
and t
h(A_NWE)
h(Data_NWE)
In
Table 33: Asynchronous multiplexed PSRAM/NOR read
t
and t
h(AD_NADV)
h(A_NOE)
In
Table 34: Asynchronous multiplexed PSRAM/NOR write
t
modified.
h(A_NWE)
In
Table 35: Synchronous multiplexed NOR/PSRAM read
t
modified.
h(CLKH-NWAITV)
In
Table 40: Switching characteristics for NAND Flash read and write
cycles: t
modified.
h(NOE-D)
Table 53: SPI characteristics
characteristics
and
Table 55: SD / MMC
C
and R
parameters modified in
ADC
AIN
R
max values modified in
AIN
Table 63: DAC characteristics
buffered DAC
added.
Figure 64: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline
and
Table 67: LFBGA100 - 10 x 10 mm low profile fine
pitch ball grid array package mechanical data
Number of DACs corrected in
I
updated in
Table 17: Typical and maximum current
DD_VBAT
consumptions in Stop and Standby
Figure 16: Typical current consumption on VBAT with RTC on vs.
7
temperature at different VBAT values
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in
Section 5.3.11: EMC characteristics on page
Table 63: DAC characteristics
Doc ID 14611 Rev 8
Changes
updated.
added in
Table 5: High-density
Table 13: Embedded internal reference
Table 23: HSE 4-16 MHz oscillator
modified. Conditions
timings.
characteristics.
modified.
modified.
modified.
timings:
modified.
timings:
timings:
modified. Values added to
Table 54: I2S
characteristics.
Table 59: ADC
characteristics.
Table 60: RAIN max for fADC = 14
modified.
Figure 61: 12-bit buffered /non-
updated.
Table 3: STM32F103xx
family.
modes.
added.
modified. Small text changes.
MHz.
83.