STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 13

• Manufacturer Part Number: STM32F103ZC
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103ZC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F103xC, STM32F103xD, STM32F103xE
Figure 2.
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
OSC32_OUT
OSC32_IN
OSC_OUT
64 MHz.
OSC_IN
MCO
Clock tree
4-16 MHz
32.768 kHz
HSE OSC
Main
Clock Output
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
PLLXTPRE
PLL
/2
/128
LSE
LSI
/2
RTCSEL[1:0]
/2
HSE
SYSCLK
PLLCLK
HSI
Doc ID 14611 Rev 8
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
72 MHz
to RTC
max
IWDGCLK
Prescaler
/1, 2..512
AHB
Prescaler
Peripheral clock
enable
Peripheral clock
enable
/1, 1.5
USB
/1, 2, 4, 8, 16
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
/1, 2, 4, 8, 16
If (APB2 prescaler =1) x1
TIM1 & 8 timers
Peripheral clock
enable
Peripheral clock
enable
/8
Prescaler
Prescaler
72 MHz max
APB2
APB1
Prescaler
/2, 4, 6, 8
FLITFCLK
to Flash programming interface
Clock
/2
Enable (4 bits)
ADC
48 MHz
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
Legend:
I2S3CLK
I2S2CLK
Peripheral clock
enable
else x2
72 MHz max
else x2
36 MHz max
ADCCLK
Peripheral Clock
Peripheral Clock
Enable (20 bits)
Enable (15 bits)
USBCLK
to USB interface
Peripheral Clock
Enable (6 bits)
HCLK
to AHB bus, core,
memory and DMA
FCLK Cortex
free running clock
to I2S3
to I2S2
to Cortex System timer
Peripheral Clock
Enable (2 bit)
To SDIO AHB interface
FSMCCLK
SDIOCLK
HCLK/2
to TIM2,3,4,5,6 and 7
TIMxCLK
TIMXCLK
peripherals to APB2
PCLK1
PCLK2
to APB1
peripherals
to ADC1, 2 or 3
to FSMC
Description
to TIM1 and TIM8
to SDIO
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