STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 52

• Manufacturer Part Number: STM32F103ZC
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103ZC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

Electrical characteristics
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Typical current consumption
The MCU is placed under the following conditions:
●
●
●
●
●
When the peripherals are enabled f
Table 18.
1. Typical values are measures at T
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
3. External clock is 8 MHz and PLL is on when f
I
Symbol
DD
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All I/O pins are in input mode with a static value at V
All peripherals are disabled except if it is explicitly mentioned.
The
wait state from 24 to 48 MHZ and 2 wait states above).
Ambient temperature and V
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
Flash
Supply
current in
Run mode
Parameter
Typical current consumption in Run mode, code with data processing
running from Flash
access time is adjusted to f
External clock
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
Conditions
A
Doc ID 14611 Rev 8
= 25 °C, V
DD
PCLK1
(3)
supply voltage conditions summarized in
HCLK
DD
= f
HCLK
= 3.3 V.
STM32F103xC, STM32F103xD, STM32F103xE
72 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
64 MHz
48 MHz
36 MHz
24 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
> 8 MHz.
HCLK
f
HCLK
frequency (0 wait state from 0 to 24 MHz, 1
/4, f
PCLK
All peripherals
enabled
DD
2 = f
34.6
26.6
18.5
12.8
17.9
12.2
7.2
4.2
2.7
1.6
1.3
6.6
3.6
2.1
1.4
0.7
51
45
34
26
2
1
or V
HCLK
(2)
SS
Typ
/2, f
(no load).
(1)
All peripherals
ADCCLK
disabled
30.5
20.7
16.2
11.4
20.1
15.6
10.8
8.2
3.1
2.1
1.7
1.4
1.2
7.6
4.4
2.5
1.5
1.1
0.8
0.6
27
5
Table
= f
PCLK2
10.
Unit
mA
mA
/4