STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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Page 80/130

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Electrical characteristics
Table 39.
Switching characteristics for PC Card/CF read and write cycles
Symbol
t
FSMC_NIOWR low width
w(NIOWR)
t
FSMC_NIOWR low to FSMC_D[15:0] valid
v(NIOWR-D)
t
FSMC_NIOWR high to FSMC_D[15:0] invalid
h(NIOWR-D)
t
FSMC_NCE4_1 low to FSMC_NIOWR valid
d(NCE4_1-NIOWR)
t
FSMC_NCEx high to FSMC_NIOWR invalid
h(NCEx-NIOWR)
t
FSMC_NCE4_1 high to FSMC_NIOWR invalid
h(NCE4_1-NIOWR)
t
FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
d(NIORD-NCEx)
t
low to FSMC_NIORD valid
d(NIORD-NCE4_1)
t
FSMC_NCEx high to FSMC_NIORD invalid
h(NCEx-NIORD)
t
FSMC_NCE4_1 high to FSMC_NIORD invalid
h(NCE4_1-NIORD)
t
FSMC_D[15:0] valid before FSMC_NIORD high
su(D-NIORD)
t
FSMC_D[15:0] valid after FSMC_NIORD high
d(NIORD-D)
t
FSMC_NIORD low width
w(NIORD)
1. C
= 15 pF.
L
2. Based on characterization, not tested in production.
NAND controller waveforms and timings
Figure 38
through
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
80/130
STM32F103xC, STM32F103xD, STM32F103xE
Parameter
Figure 41
represent synchronous waveforms and
Doc ID 14611 Rev 8
(1)(2)
(continued)
Min
Max
Unit
8t
+ 3
ns
HCLK
5t
+1
ns
HCLK
11t
ns
HCLK
5t
+3ns
ns
HCLK
5t
– 5
ns
HCLK
5t
+ 2.5
ns
HCLK
5t
– 5
ns
HCLK
4.5
ns
9
ns
8t
+ 2
ns
HCLK
Table 40
provides the