STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 


Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
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STM32F103xC, STM32F103xD, STM32F103xE
5.3.17
Communications interfaces
2
I
C interface characteristics
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
Table
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
performance line I
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V
is disabled, but is still present.
DD
2
The I
C characteristics are described in
for more details on the input/output alternate function characteristics (SDA
characteristics
and SCL) .
2
Table 51.
I
C characteristics
Symbol
t
SCL clock low time
w(SCLL)
t
SCL clock high time
w(SCLH)
t
SDA setup time
su(SDA)
t
SDA data hold time
h(SDA)
t
r(SDA)
SDA and SCL rise time
t
r(SCL)
t
f(SDA)
SDA and SCL fall time
t
f(SCL)
t
Start condition hold time
h(STA)
Repeated Start condition
t
su(STA)
setup time
t
Stop condition setup time
su(STO)
Stop to Start condition time
t
w(STO:STA)
(bus free)
Capacitive load for each bus
C
b
line
1. Guaranteed by design, not tested in production.
2. f
must be higher than 2 MHz to achieve standard mode I
PCLK1
to achieve the fast mode I
mode maximum clock speed of 400 kHz.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
frequency and V
PCLK1
10.
2
C interface meets the requirements of the standard I
Table
51. Refer also to
Standard mode I
Parameter
Min
4.7
4.0
250
(3)
0
4.0
4.7
4.0
4.7
2
C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
Doc ID 14611 Rev 8
Electrical characteristics
Table 51
are derived from tests
supply voltage conditions
DD
2
C communication
Section 5.3.14: I/O port
2
(1)
2
(1)(2)
C
Fast mode I
C
Max
Min
Max
1.3
0.6
100
(4)
(3)
0
900
1000
20 + 0.1C
300
b
300
300
0.6
0.6
0.6
1.3
400
400
2
C frequencies. It must be higher than 4 MHz
Unit
µs
ns
µs
μs
μs
pF
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