STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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STM32F103xC, STM32F103xD, STM32F103xE
2
I
S - SPI characteristics
Unless otherwise specified, the parameters given in
are derived from tests performed under ambient temperature, f
supply voltage conditions summarized in
Refer to
Section 5.3.14: I/O port characteristics
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 53.
SPI characteristics
Symbol
f
SCK
SPI clock frequency
1/t
c(SCK)
t
SPI clock rise and fall
r(SCK)
t
time
f(SCK)
SPI slave input clock duty
DuCy(SCK)
cycle
(1)
t
NSS setup time
su(NSS)
(1)
t
NSS hold time
h(NSS)
(1)
t
w(SCKH)
SCK high and low time
(1)
t
w(SCKL)
(1)
t
su(MI)
Data input setup time
(1)
t
su(SI)
(1)
t
h(MI)
Data input hold time
(1)
t
h(SI)
(1)(2)
t
Data output access time
a(SO)
(1)(3)
t
Data output disable time
dis(SO)
(1)
t
Data output valid time
v(SO)
(1)
t
Data output valid time
v(MO)
(1)
t
h(SO)
Data output hold time
(1)
t
h(MO)
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Table
10.
for more details on the input/output alternate
Parameter
Conditions
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Doc ID 14611 Rev 8
Electrical characteristics
Table 53
for SPI or in
Table 54
frequency and V
PCLKx
2
S).
Min
Max
18
18
30
70
4t
PCLK
2t
PCLK
= 36 MHz,
PCLK
50
60
5
5
5
4
= 20 MHz
0
3t
PCLK
PCLK
2
10
25
5
15
2
2
for I
S
DD
Unit
MHz
8
ns
%
ns
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