STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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Page 98/130

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Electrical characteristics
2
Table 54.
I
S characteristics
Symbol
Parameter
I2S slave input clock duty
DuCy(SCK)
cycle
f
2
CK
I
S clock frequency
1/t
c(CK)
t
2
r(CK)
I
S clock rise and fall time
t
f(CK)
(1)
t
WS valid time
v(WS)
(1)
t
WS hold time
h(WS)
(1)
t
WS setup time
su(WS)
(1)
t
WS hold time
h(WS)
(1)
t
w(CKH)
CK high and low time
(1)
t
w(CKL)
(1)
t
Data input setup time
su(SD_MR)
(1)
t
Data input setup time
su(SD_SR)
(1)(2)
t
h(SD_MR)
Data input hold time
(1)(2)
t
h(SD_SR)
(1)(2)
t
Data output valid time
v(SD_ST)
(1)
t
Data output hold time
h(SD_ST)
(1)(2)
t
Data output valid time
v(SD_MT)
(1)
t
Data output hold time
h(SD_MT)
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on f
. For example, if f
PCLK
98/130
STM32F103xC, STM32F103xD, STM32F103xE
Conditions
Slave mode
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
Slave mode
Capacitive load C
= 50 pF
L
Master mode
Master mode
Slave mode
Slave mode
Master f
= 16 MHz, audio
PCLK
frequency = 48 kHz
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable
edge)
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
Master transmitter (after enable
edge)
=8 MHz, then T
= 1/f
=125 ns.
PCLK
PCLK
PLCLK
Doc ID 14611 Rev 8
Min
Max
30
70
1.522
1.525
0
6.5
8
3
I2S2
2
I2S3
0
4
0
312.5
345
I2S2
2
I2S3
6.5
1.5
0
0.5
18
11
3
0
Unit
%
MHz
ns