STM32F101RG STMicroelectronics, STM32F101RG Datasheet - Page 15

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STM32F101RG

Manufacturer Part Number
STM32F101RG
Description
Mainstream Access line, ARM Cortex-M3 MCU with 1 Mbyte Flash, 36 MHz CPU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F101RG

Conversion Range
0 to 3.6 V
Peripherals Supported
timers, ADC, DAC, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter

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STM32F101xF, STM32F101xG
2.3
2.3.1
2.3.2
2.3.3
2.3.4
Overview
ARM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F101xF and STM32F101xG access line family having an embedded ARM core,
is therefore compatible with all ARM tools and software.
Figure 1
Memory protection unit
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Embedded Flash memory
768 Kbytes to 1 Mbyte of embedded Flash are available for storing programs and data. The
Flash memory is organized as two banks. The first bank has a size of 512 Kbytes. The
second bank is either 256 or 512 Kbytes depending on the device. This gives the device the
capability of writing to one bank while executing code from the other bank (read-while-write
capability).
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
®
Cortex™-M3 core with embedded Flash and SRAM
shows the general block diagram of the device family.
Doc ID 17143 Rev 2
Description
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