STM32F101RG STMicroelectronics, STM32F101RG Datasheet - Page 67

• Manufacturer Part Number: STM32F101RG
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 1 Mbyte Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101RG

• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, DAC, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F101xF, STM32F101xG
Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings
Table 37.
1. C
2. Preliminary values.
t
t
t
t
t
t
t
t
t
t
t
t
t
w(CLK)
d(CLKL-NExL)
d(CLKH-NExH)
d(CLKL-NADVL)
d(CLKL-NADVH)
d(CLKL-AV)
d(CLKH-AIV)
d(CLKL-NOEL)
d(CLKH-NOEH)
su(DV-CLKH)
h(CLKH-DV)
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_D[15:0]
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_A[25:0]
FSMC_NADV
FSMC_CLK
FSMC_NOE
Symbol
FSMC_NEx
L
t d(CLKL-NADVL)
t d(CLKL-NExL)
= 15 pF.
Synchronous non-multiplexed NOR/PSRAM read timings
t w(CLK)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x = 0...25)
FSMC_CLK high to FSMC_Ax invalid (x = 0...25) T
FSMC_CLK low to FSMC_NOE low
FSMC_CLK high to FSMC_NOE high
FSMC_D[15:0] valid data before FSMC_CLK high 6.5
FSMC_D[15:0] valid data after FSMC_CLK high
FSMC_NWAIT valid before FSMC_SMCLK high
FSMC_NWAIT valid after FSMC_CLK high
t d(CLKL-AV)
Doc ID 17143 Rev 2
t su(NWAITV-CLKH)
t su(NWAITV-CLKH)
t d(CLKL-NADVH)
Parameter
t su(DV-CLKH)
Data latency = 1
t w(CLK)
t su(NWAITV-CLKH)
t d(CLKL-NOEL)
D1
t su(DV-CLKH)
t h(CLKH-DV)
t h(CLKH-NWAITV)
t h(CLKH-NWAITV)
t d(CLKH-NOEH)
27.7
T
5
T
7
7
2
t d(CLKH-NExH)
HCLK
HCLK
HCLK
t d(CLKH-AIV)
Electrical characteristics
t h(CLKH-NWAITV)
Min
D2
BUSTURN = 0
+ 2
+ 4
+ 1.5
t h(CLKH-DV)
(1)(2)
1.5
4
0
T
HCLK
Max
+ 1.5 ns
ai14894d
67/108
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns