STM32F103VF

Manufacturer Part NumberSTM32F103VF
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 768 Kbytes Flash, 72MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103VF datasheet
 


Specifications of STM32F103VF

Conversion Range0 to 3.6 VSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Page 1/120

Download datasheet (3Mb)Embed
Next
XL-density performance line ARM-based 32-bit MCU with 768 KB to
1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 communication interfaces
Features
Core: ARM 32-bit Cortex™-M3 CPU with MPU
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
Memories
– 768 Kbytes to 1 Mbyte of Flash memory
– 96 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
supply for RTC and backup registers
BAT
3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
2 × 12-bit D/A converters
DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
2
2
SDIO, I
Ss, SPIs, I
Cs and USARTs
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™
January 2012
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Up to 17 timers
– Up to ten 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 × 16-bit motor control PWM timers with
dead-time generation and emergency stop
– 2 × watchdog timers (Independent and
Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
Up to 13 communication interfaces
2
– Up to 2 × I
C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I
interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
CRC calculation unit, 96-bit unique ID
®
ECOPACK
packages
Table 1.
Device summary
Reference
STM32F103RF STM32F103VF
STM32F103xF
STM32F103ZF
STM32F103RG STM32F103VG
STM32F103xG
STM32F103ZG
Doc ID 16554 Rev 3
STM32F103xF
STM32F103xG
Target specification
FBGA
LFBGA144 10 × 10 mm
2
S
Part number
1/120
www.st.com
1

STM32F103VF Summary of contents

  • Page 1

    ... USB 2.0 full speed interface – SDIO interface ■ CRC calculation unit, 96-bit unique ID ® ■ ECOPACK packages Table 1. Device summary Reference STM32F103RF STM32F103VF STM32F103xF STM32F103ZF STM32F103RG STM32F103VG STM32F103xG STM32F103ZG Doc ID 16554 Rev 3 STM32F103xF STM32F103xG Target specification FBGA LFBGA144 10 × ...

  • Page 2

    Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    STM32F103xF, STM32F103xG 2.3.29 2.3.30 2.3.31 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Contents 5.3.19 5.3.20 5.3.21 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    STM32F103xF, STM32F103xG List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    List of tables Table 44. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    STM32F103xF, STM32F103xG List of figures Figure 1. STM32F103xF and STM32F103xG performance line block diagram Figure 2. Clock tree . . . . . ...

  • Page 8

    List of figures Figure 40. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 9

    ... This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the The XL-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual ...

  • Page 10

    Description 2 Description The STM32F103xF and STM32F103xG performance line family incorporates the high- performance ARM speed embedded memories (Flash memory Mbyte and SRAM Kbytes), and an extensive range of enhanced I/Os and peripherals connected ...

  • Page 11

    STM32F103xF, STM32F103xG 2.1 Device overview The STM32F103xx XL-density performance line family offers devices in four different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an ...

  • Page 12

    Description Figure 1. STM32F103xF and STM32F103xG performance line block diagram TRACECLK TRACED[0:3] TPIU ETM as AF Trace/Trig SWJTAG NJTRST JTDI MPU JTCK/SWCLK JTMS/SWDAT JTDO Cortex-M3 CPU 48/72 MHz max NVIC NVIC GP DMA1 7 channels GP ...

  • Page 13

    STM32F103xF, STM32F103xG Figure 2. Clock tree 8 MHz HSI RC OSC_OUT 4-16 MHz HSE OSC OSC_IN OSC32_IN LSE OSC 32.768 kHz OSC32_OUT LSI RC 40 kHz Main Clock Output MCO 1. When the HSI is used as a PLL clock ...

  • Page 14

    Description 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are ...

  • Page 15

    STM32F103xF, STM32F103xG 2.3 Overview ® 2.3.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the ...

  • Page 16

    Description 2.3.5 Embedded SRAM 96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.6 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family. It has four ...

  • Page 17

    STM32F103xF, STM32F103xG 2.3.10 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it ...

  • Page 18

    Description 2.3.14 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● used in the nominal regulation mode (Run) ● LPR is used in the Stop modes. ● Power down is ...

  • Page 19

    STM32F103xF, STM32F103xG The DMA can be used with the main peripherals: SPI, I and advanced-control timers TIMx, DAC, I 2.3.17 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power ...

  • Page 20

    Description Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as ...

  • Page 21

    STM32F103xF, STM32F103xG Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit ...

  • Page 22

    Description 2.3.21 Serial peripheral interface (SPI three SPIs are able to communicate Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame ...

  • Page 23

    STM32F103xF, STM32F103xG The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.27 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xF ...

  • Page 24

    Description 2.3.29 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V connected to the ADC1_IN16 input channel which is used to convert the sensor output ...

  • Page 25

    STM32F103xF, STM32F103xG 3 Pinouts and pin descriptions Figure 3. STM32F103xF and STM32F103xG XL-density performance line BGA144 ballout PC13- PE3 PE2 A TAMPER-RTC PC14- B PE4 PE5 OSC32_IN PC15 BAT PF0 OSC32_OUT D OSC_IN V SS_5 ...

  • Page 26

    Pinouts and pin descriptions Figure 4. STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 PF3 13 ...

  • Page 27

    STM32F103xF, STM32F103xG Figure 5. STM32F103xF and STM32F103xG XL-density performance line LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

  • Page 28

    Pinouts and pin descriptions Figure 6. STM32F103xF and STM32F103xG XL-density performance line LQFP64 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT 28/120 VBAT PD0 ...

  • Page 29

    STM32F103xF, STM32F103xG Table 5. STM32F103xF and STM32F103xG pin definitions Pins Pin name PE2 PE3 PE4 PE5 PE6 ...

  • Page 30

    Pinouts and pin descriptions Table 5. STM32F103xF and STM32F103xG pin definitions (continued) Pins Pin name REF DDA PA0-WKUP PA1 ...

  • Page 31

    STM32F103xF, STM32F103xG Table 5. STM32F103xF and STM32F103xG pin definitions (continued) Pins Pin name PF14 PF15 PG0 PG1 PE7 L7 - ...

  • Page 32

    Pinouts and pin descriptions Table 5. STM32F103xF and STM32F103xG pin definitions (continued) Pins Pin name K10 - 60 82 PD13 SS_8 DD_8 K11 - 61 85 PD14 K12 - 62 ...

  • Page 33

    STM32F103xF, STM32F103xG Table 5. STM32F103xF and STM32F103xG pin definitions (continued) Pins Pin name A10 50 77 110 PA15 B11 51 78 111 PC10 B10 52 79 112 PC11 C10 53 80 113 PC12 E10 - 81 114 PD0 D10 - ...

  • Page 34

    ... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For devices delivered in LQFP64 packages, the FSMC function is not available. ...

  • Page 35

    STM32F103xF, STM32F103xG Table 6. FSMC pin definition Pins CF PE2 PE3 PE4 PE5 PE6 PF0 A0 PF1 A1 PF2 A2 PF3 A3 PF4 A4 PF5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF11 NIOS16 PF12 A6 ...

  • Page 36

    Pinouts and pin descriptions Table 6. FSMC pin definition (continued) Pins CF PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 NWAIT ...

  • Page 37

    STM32F103xF, STM32F103xG 4 Memory mapping The memory map is shown in Figure 7. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 0x4000 0000 0x3FFF ...

  • Page 38

    Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 39

    STM32F103xF, STM32F103xG 5.1.6 Power supply scheme Figure 10. Power supply scheme Caution: In Figure 10, the 4.7 µF capacitor must be connected to V 5.1.7 Current consumption measurement Figure 11. Current consumption measurement scheme DD3 BAT V ...

  • Page 40

    Electrical characteristics 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. ...

  • Page 41

    STM32F103xF, STM32F103xG Table 9. Thermal characteristics Symbol T STG T J 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol f Internal AHB clock frequency HCLK f Internal APB1 clock frequency PCLK1 f Internal APB2 clock ...

  • Page 42

    Electrical characteristics 5.3.2 Operating conditions at power-up / power-down The parameters given in temperature condition summarized in Table 11. Operating conditions at power-up / power-down Symbol V rise time rate DD t VDD V fall time rate DD 5.3.3 Embedded ...

  • Page 43

    STM32F103xF, STM32F103xG 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 13. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

  • Page 44

    Electrical characteristics Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 MHz ...

  • Page 45

    STM32F103xF, STM32F103xG Figure 12. Typical current consumption in Run mode versus frequency (at 3 code with data processing running from RAM, peripherals enabled Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V)- code with ...

  • Page 46

    Electrical characteristics Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock is 8 MHz ...

  • Page 47

    STM32F103xF, STM32F103xG Table 17. Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Regulator in run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog), Supply current MHz CK ...

  • Page 48

    Electrical characteristics Figure 15. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V 48/120 STM32F103xF, STM32F103xG values DD Doc ID 16554 Rev 3 ...

  • Page 49

    STM32F103xF, STM32F103xG Figure 16. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V Figure 17. Typical current consumption in Standby mode versus temperature at different V values DD Doc ID 16554 Rev 3 ...

  • Page 50

    Electrical characteristics Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at V ● All peripherals are disabled except explicitly mentioned. ● The ...

  • Page 51

    STM32F103xF, STM32F103xG Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of 0.8 ...

  • Page 52

    Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● all I/O pins are in input mode with a static value at V ● all peripherals are disabled unless ...

  • Page 53

    STM32F103xF, STM32F103xG Table 20. Peripheral current consumption Peripheral APB2 MHz, f HCLK 2. Specific conditions for DAC: EN1, EN2 bits in the DAC_CR register are set to 1 and the converted value set to 0x800. 3. ...

  • Page 54

    Electrical characteristics Table 21. High-speed external user clock characteristics Symbol User external clock source f HSE_ext frequency V OSC_IN input pin high level voltage HSEH V OSC_IN input pin low level voltage HSEL t w(HSE) OSC_IN high or low time ...

  • Page 55

    STM32F103xF, STM32F103xG Figure 18. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) EXTER NAL CLOCK SOURC E Figure 19. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t ...

  • Page 56

    Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained ...

  • Page 57

    STM32F103xF, STM32F103xG Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical ...

  • Page 58

    Electrical characteristics Figure 21. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors 5.3.7 Internal clock source characteristics The parameters given in temperature and V High-speed internal (HSI) RC oscillator Table 25. HSI oscillator ...

  • Page 59

    STM32F103xF, STM32F103xG Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics Symbol (2) f Frequency LSI (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 to ...

  • Page 60

    Electrical characteristics 5.3.8 PLL characteristics The parameters given in temperature and V Table 28. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT t PLL lock time LOCK Jitter Cycle-to-cycle ...

  • Page 61

    STM32F103xF, STM32F103xG Table 30. Flash memory endurance and data retention Symbol Parameter N Endurance END t Data retention RET 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms ...

  • Page 62

    Electrical characteristics Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Note: FSMC_BusTurnAroundDuration = 0. 62/120 STM32F103xF, STM32F103xG Doc ID 16554 Rev 3 ...

  • Page 63

    STM32F103xF, STM32F103xG Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low time w(NOE) t FSMC_NOE high to FSMC_NE high hold time h(NE_NOE) t FSMC_NEx low to ...

  • Page 64

    Electrical characteristics Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low time w(NWE) t FSMC_NWE high to FSMC_NE high hold time h(NE_NWE) t FSMC_NEx low to ...

  • Page 65

    STM32F103xF, STM32F103xG Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 34. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low ...

  • Page 66

    Electrical characteristics Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 35. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...

  • Page 67

    STM32F103xF, STM32F103xG Synchronous waveforms and timings Figure 26 through Table 39 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...

  • Page 68

    Electrical characteristics Table 36. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low ...

  • Page 69

    STM32F103xF, STM32F103xG Figure 27. Synchronous multiplexed PSRAM write timings Doc ID 16554 Rev 3 Electrical characteristics 69/120 ...

  • Page 70

    Electrical characteristics Table 37. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t d(CLKL-NBLH ...

  • Page 71

    STM32F103xF, STM32F103xG Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings Table 38. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) ...

  • Page 72

    Electrical characteristics Figure 29. Synchronous non-multiplexed PSRAM write timings Table 39. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t d(CLKL-NBLH) 1. ...

  • Page 73

    STM32F103xF, STM32F103xG PC Card/CompactFlash controller waveforms and timings Figure 30 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime ...

  • Page 74

    Electrical characteristics Figure 31. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 74/120 High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID ...

  • Page 75

    STM32F103xF, STM32F103xG Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High t ...

  • Page 76

    Electrical characteristics Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 34. PC Card/CompactFlash controller ...

  • Page 77

    STM32F103xF, STM32F103xG Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access Table 40. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol t FSMC_NCEx low to FSMC_Ay valid v(NCEx-A) t FSMC_NCEx high to FSMC_Ax ...

  • Page 78

    Electrical characteristics Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol tw FSMC_NIOWR low width (NIOWR) tv FSMC_NIOWR low to FSMC_D[15:0] valid (NIOWR-D) th FSMC_NIOWR high to FSMC_D[15:0] invalid (NIOWR-D) td FSMC_NCE4_1 low to ...

  • Page 79

    STM32F103xF, STM32F103xG Figure 36. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 37. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 38. NAND controller ...

  • Page 80

    Electrical characteristics Figure 39. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 42. Switching characteristics for NAND Flash read cycles Symbol t FSMC_NOE low width w(NOE) FSMC_D[15:0] valid data before FSMC_NOE ...

  • Page 81

    STM32F103xF, STM32F103xG 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by ...

  • Page 82

    Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD ...

  • Page 83

    STM32F103xF, STM32F103xG Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and ...

  • Page 84

    Electrical characteristics 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 49. I/O static characteristics Symbol Parameter Standard IO input low level voltage V IL (1) IO ...

  • Page 85

    STM32F103xF, STM32F103xG Figure 40. Standard I/O input characteristics - CMOS port Figure 41. Standard I/O input characteristics - TTL port Doc ID 16554 Rev 3 Electrical characteristics 85/120 ...

  • Page 86

    Electrical characteristics Figure 42 tolerant I/O input characteristics - CMOS port Figure 43 tolerant I/O input characteristics - TTL port Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...

  • Page 87

    STM32F103xF, STM32F103xG Output voltage levels Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. All I/Os are CMOS and TTL compliant. Table 50. Output voltage characteristics Symbol Output low level voltage for an I/O ...

  • Page 88

    Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 51, respectively. Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. Table 51. I/O AC characteristics MODEx[1:0] ...

  • Page 89

    STM32F103xF, STM32F103xG Figure 44. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved £ 2/3)T and if the duty cycle is (45-55%) 5.3.15 NRST pin characteristics The NRST pin ...

  • Page 90

    Electrical characteristics 5.3.16 TIM timer characteristics The parameters given in Refer to Section 5.3.14: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 53. TIMx Symbol t Timer resolution time res(TIM) Timer external clock f ...

  • Page 91

    STM32F103xF, STM32F103xG 5.3.17 Communications interfaces interface characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I protocol with the following restrictions: ...

  • Page 92

    Electrical characteristics 2 Figure 46 bus AC waveforms and measurement circuit bus S TART SDA t r(SDA) t f(SDA) t h(STA) SCL t w(SCLH) 1. Measurement points are done at CMOS levels: 0.3V Table 55. ...

  • Page 93

    STM32F103xF, STM32F103xG SPI characteristics Unless otherwise specified, the parameters given in are derived from tests performed under ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.14: I/O port characteristics function characteristics (NSS, SCK, ...

  • Page 94

    Electrical characteristics Figure 47. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

  • Page 95

    STM32F103xF, STM32F103xG Figure 49. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V (1) ...

  • Page 96

    Electrical characteristics 2 Table 57 characteristics Symbol Parameter DuCy(SCK) I2S slave input clock duty cycle Slave mode clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ...

  • Page 97

    STM32F103xF, STM32F103xG 2 Figure 50 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...

  • Page 98

    Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table Refer to Section 5.3.14: I/O port characteristics function characteristics (D[7:0], CMD, CK). Figure 52. SDIO high-speed ...

  • Page 99

    STM32F103xF, STM32F103xG Table 58 MMC characteristics Symbol Clock frequency in data transfer f PP mode t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time r t Clock fall time f CMD, ...

  • Page 100

    Electrical characteristics Table 60. USB DC electrical characteristics Symbol Input levels V USB operating voltage DD (4) V Differential input sensitivity DI (4) V Differential common mode range Includes V CM (4) V Single ended receiver threshold SE Output levels ...

  • Page 101

    STM32F103xF, STM32F103xG 5.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in from tests performed under ambient temperature, f conditions summarized in Note recommended to perform a calibration after each power-up. Table 62. ADC characteristics Symbol Parameter ...

  • Page 102

    Electrical characteristics Equation 1: R AIN < R --------------------------------------------------------------- - R AIN × ADC The formula above allowed for an error below 1/4 of LSB. Here (from 12-bit resolution). Table 63. R AIN T (cycles) ...

  • Page 103

    STM32F103xF, STM32F103xG Table 65. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be ...

  • Page 104

    Electrical characteristics Figure 56. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance ...

  • Page 105

    STM32F103xF, STM32F103xG Figure 58. Power supply and reference decoupling ( and V REF+ REF– 1 µ inputs are available only on 100-pin packages. Doc ID 16554 Rev 3 Electrical characteristics V ) connected to REF+ ...

  • Page 106

    Electrical characteristics 5.3.20 DAC electrical specifications Table 66. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA Resistive load vs. V SSA buffer ON (1) R LOAD Resistive load vs. V DDA ...

  • Page 107

    STM32F103xF, STM32F103xG Table 66. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (2) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...

  • Page 108

    Electrical characteristics 5.3.21 Temperature sensor characteristics Table 67. TS characteristics Symbol ( SENSE (1) Avg_Slope Average slope (1) V Voltage at 25 °C 25 (2) t Startup time START ADC sampling time when reading the (3)(2) T ...

  • Page 109

    STM32F103xF, STM32F103xG 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

  • Page 110

    Package characteristics Figure 61. LFBGA144 – 144-ball low profile fine pitch ball grid array mm, 0.8 mm pitch, package outline 1. Drawing is not to scale. Table 68. LFBGA144 – 144-ball low profile fine pitch ball grid ...

  • Page 111

    STM32F103xF, STM32F103xG Figure 62. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to scale. ...

  • Page 112

    Package characteristics Figure 64. LQFP100 100-pin low-profile quad flat package outline 100 26 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in ...

  • Page 113

    STM32F103xF, STM32F103xG Figure 66. LQFP64 – pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. Dimensions ...

  • Page 114

    Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 10: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: ● T max is the maximum ambient temperature in °C, A Θ ...

  • Page 115

    STM32F103xF, STM32F103xG 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation ...

  • Page 116

    Package characteristics Using the values obtained in – For LQFP100, 46 °C 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C Jmax This is within the range of the suffix ...

  • Page 117

    STM32F103xF, STM32F103xG 7 Part numbering Table 73. STM32F103xF and STM32F103xG ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count pins V = ...

  • Page 118

    Revision history 8 Revision history Table 74. Document revision history Date Revision 27-Oct-2009 15-Nov-2010 18-Jan-2012 118/120 1 Initial release. LQFP64 package mechanical data updated: see pin low-profile quad flat package outline LQFP64 – ...

  • Page 119

    STM32F103xF, STM32F103xG Table 74. Document revision history Date Revision 18-Jan-2012 Asynchronous waveforms and period and FSMC_BusTurnAroundDuration; updated conditions, modified Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings, Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write PSRAM/NOR read timings, and PSRAM/NOR write timings; added ...

  • Page 120

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...