STM32F101ZE STMicroelectronics, STM32F101ZE Datasheet
STM32F101ZE
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STM32F101ZE Summary of contents
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... CRC calculation unit, 96-bit unique ID ® ■ ECOPACK packages Table 1. Device summary Reference STM32F101RC STM32F101VC STM32F101xC STM32F101ZC STM32F101RD STM32F101VD STM32F101xD STM32F101ZD STM32F101RE STM32F101ZE STM32F101xE STM32F101VE Doc ID 14610 Rev 8 STM32F101xE LQFP100 LQFP64 × × Part number 1/112 www.st.com ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F101xC, STM32F101xD, STM32F101xE 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.2.1 6.2.2 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F101xC, STM32F101xD, STM32F101xE List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F101xC, STM32F101xD, STM32F101xE List of figures Figure 1. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram . . . . . . . . 12 Figure 2. Clock tree . . . . . . . . . . . ...
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List of figures Figure 41 tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xC, STM32F101xD and STM32F101xE high-density access line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the The high-density STM32F101xx datasheet should be read in conjunction with the STM32F10xxx reference manual ...
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Description 2 Description The STM32F101xC, STM32F101xD and STM32F101xE access line family incorporates the high-performance ARM high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM Kbytes), and an extensive range of enhanced I/Os and peripherals connected ...
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STM32F101xC, STM32F101xD, STM32F101xE 2.1 Device overview The STM32F101xx high-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives ...
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Description Figure 1. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram TRACECLK TRACED[0:3] TPIU as AS SW/JTAG NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT 112AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 2. Clock tree 8 MHz HSI RC PLLSRC OSC_OUT 4-16 MHz HSE OSC OSC_IN OSC32_IN LSE OSC 32.768 kHz OSC32_OUT LSI RC 40 kHz Main Clock Output MCO 1. When the HSI is used as a ...
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Description 2.2 Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are ...
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STM32F101xC, STM32F101xD, STM32F101xE The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xC, STM32F101xD and STM32F101xE access line family having ...
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Description 2.3.7 Nested vectored interrupt controller (NVIC) The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested vectored interrupt controller able to handle maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority ...
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STM32F101xC, STM32F101xD, STM32F101xE 2.3.11 Power supply schemes ● 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. DD Provided externally through V ● SSA DDA RCs and PLL (minimum voltage to ...
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Description The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. ● Standby mode The Standby ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 4. Timer feature comparison Counter Timer resolution TIM2, TIM3, 16-bit TIM4, TIM5 TIM6, 16-bit TIM7 General-purpose timers (TIMx) There are synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xC, STM32F101xD ...
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Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: ● A 24-bit down counter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches ...
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STM32F101xC, STM32F101xD, STM32F101xE 2.3.22 ADC (analog to digital converter) A 12-bit analog-to-digital converter is embedded into STM32F101xC, STM32F101xD and STM32F101xE access line devices. It has external channels, performing conversions in single-shot or scan modes. In scan mode, ...
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Description 2.3.26 Embedded Trace Macrocell™ ® The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small ...
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STM32F101xC, STM32F101xD, STM32F101xE 3 Pinouts and pin descriptions Figure 3. STM32F101xC, STM32F101xD and STM32F101xE access line LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-TAMPER-RTC 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 ...
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Pinouts and pin descriptions Figure 4. STM32F101xC, STM32F101xD and STM32F101xE LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP 24/112 STM32F101xC, STM32F101xD, STM32F101xE PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 5. STM32F101xC, STM32F101xD and STM32F101xE LQFP64 pinout V BAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST PC0 PC1 PC2 PC3 V SSA V DDA PA0-WKUP PA1 PA2 Table 5. High-density STM32F101xx pin definitions Pins Pin name 1 ...
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Pinouts and pin descriptions Table 5. High-density STM32F101xx pin definitions (continued) Pins Pin name PF6 PF7 PF8 PF9 PF10 OSC_IN 24 6 ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 5. High-density STM32F101xx pin definitions (continued) Pins Pin name PA7 PC4 PC5 PB0 PB1 PB2 ...
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Pinouts and pin descriptions Table 5. High-density STM32F101xx pin definitions (continued) Pins Pin name PB13 PB14 PB15 PD8 PD9 PD10 80 - ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 5. High-density STM32F101xx pin definitions (continued) Pins Pin name 104 45 71 PA12 105 46 72 PA13 106 - 73 107 SS_2 108 DD_2 109 49 76 PA14 110 50 ...
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... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 6. FSMC pin definition Pins CF PE2 PE3 PE4 PE5 PE6 PF0 A0 PF1 A1 PF2 A2 PF3 A3 PF4 A4 PF5 A5 PF6 NIORD PF7 NREG PF8 NIOWR PF9 CD PF10 INTR PF11 NIOS16 PF12 ...
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Pinouts and pin descriptions Table 6. FSMC pin definition (continued) Pins CF PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 NWE PD6 NWAIT ...
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STM32F101xC, STM32F101xD, STM32F101xE 4 Memory mapping The memory map is shown in Figure 6. Memory map 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 0xC000 0000 0xBFFF FFFF 0xA000 0000 0x9FFF FFFF 0x8000 0000 0x7FFF FFFF 0x6000 0000 0x5FFF FFFF 0x4000 0000 ...
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Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STM32F101xC, STM32F101xD, STM32F101xE 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Pin loading conditions C=50pF 5.1.6 Power supply scheme Figure 9. Power supply scheme Caution: In Figure 9, the ...
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Electrical characteristics 5.1.7 Current consumption measurement Figure 10. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 8. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control ...
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Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 10. General operating conditions Symbol f Internal AHB clock frequency HCLK f Internal APB1 clock frequency PCLK1 f Internal APB2 clock frequency PCLK2 V Standard operating voltage DD Analog operating ...
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STM32F101xC, STM32F101xD, STM32F101xE 5.3.3 Embedded reset and power control block characteristics The parameters given in temperature and V . Table 12. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis ...
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Electrical characteristics 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 13. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when reading (1) T S_vrefint the internal reference voltage Internal reference voltage ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 ...
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Electrical characteristics Figure 11. Typical current consumption in Run mode versus frequency (at 3 code with data processing running from RAM, peripherals enabled Figure 12. Typical current consumption in Run ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. Based on characterization, tested in production External clock is 8 ...
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Electrical characteristics Figure 13. Typical current consumption on V different V 2.5 2 1.5 1 0.5 0 Figure 14. Typical current consumption in Stop mode with regulator in run mode versus temperature at different V 300 250 200 150 100 ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 15. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different V 300 250 200 150 100 50 0 Figure 16. Typical current consumption in Standby mode versus temperature at different ...
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Electrical characteristics Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at V ● All peripherals are disabled except explicitly mentioned ● The ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of ...
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Electrical characteristics Table 20. Peripheral current consumption Peripheral APB1 APB2 48/112 STM32F101xC, STM32F101xD, STM32F101xE Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 SPI2 SPI3 USART2 USART3 UART4 UART5 I2C1 I2C2 DAC GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 20. Peripheral current consumption (continued) Peripheral APB2 MHz, f HCLK 2. Specific conditions for ADC the ADC_CR2 register is set Specific conditions for ADC the ...
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Electrical characteristics Table 21. High-speed external user clock characteristics Symbol User external clock source f HSE_ext frequency OSC_IN input pin high level V HSEH voltage OSC_IN input pin low level V HSEL voltage t w(HSE) OSC_IN high or low time ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 17. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 18. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) ...
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Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 19. Typical application with an 8 MHz crystal Resonator with integrated capacitors value depends on the crystal characteristics. EXT Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock ...
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Electrical characteristics Note: For C and recommended to use high-quality ceramic capacitors in the range selected to match the requirements of the crystal or resonator. C usually the same ...
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STM32F101xC, STM32F101xD, STM32F101xE 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) ...
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Electrical characteristics 5.3.8 PLL characteristics The parameters given in temperature and V Table 28. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT t PLL lock time LOCK Jitter Cycle-to-cycle ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 30. Flash memory endurance and data retention Symbol N Endurance END t Data retention RET 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms ...
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Electrical characteristics Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NEx low to FSMC_NADV low v(NADV_NE) t FSMC_NADV low time w(NADV pF Based on characterization, not tested in production. Figure 22. Asynchronous ...
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Electrical characteristics Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NEx low to FSMC_NADV low v(NADV_NE) t FSMC_NADV low time w(NADV pF Based on characterization, not tested in production. Figure 23. Asynchronous multiplexed ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 33. Asynchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_BL hold time after FSMC_NOE high h(BL_NOE) t FSMC_NEx low to FSMC_BL valid v(BL_NE) t Data to FSMC_NEx high setup time su(Data_NE) t Data to FSMC_NOE high setup ...
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Electrical characteristics Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 34. Asynchronous multiplexed NOR/PSRAM write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...
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STM32F101xC, STM32F101xD, STM32F101xE Synchronous waveforms and timings Figure 25 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = ...
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Electrical characteristics Table 35. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 26. Synchronous multiplexed PSRAM write timings Doc ID 14610 Rev 8 Electrical characteristics 65/112 ...
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Electrical characteristics Table 36. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH) ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings Table 37. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = ...
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Electrical characteristics Figure 28. Synchronous non-multiplexed PSRAM write timings Table 38. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t su(NWAITV-CLKH) t ...
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STM32F101xC, STM32F101xD, STM32F101xE PC Card/CompactFlash controller waveforms and timings Figure 29 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● ...
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Electrical characteristics Figure 30. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 70/112 STM32F101xC, STM32F101xD, STM32F101xE High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High ...
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Electrical characteristics Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 33. PC Card/CompactFlash controller ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NIOWR FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t d(NCE4_1-NIOWR) FSMC_NIOWR FSMC_D[15:0] Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol FSMC_NCEx low (x = ...
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Electrical characteristics Table 39. Switching characteristics for PC Card/CF read and write cycles Symbol t FSMC_D[15:0] valid before FSMC_NWE high d(D-NWE) t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 35. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 36. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 37. NAND ...
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Electrical characteristics Figure 38. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 40. Switching characteristics for NAND Flash read and write cycles Symbol (2) t FSMC_D[15:0] valid before FSMC_NWE high d(D-NWE) ...
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STM32F101xC, STM32F101xD, STM32F101xE 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed ...
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Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test ...
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STM32F101xC, STM32F101xD, STM32F101xE 5.3.13 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O pins) should be avoided during normal product DD operation. ...
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Electrical characteristics 5.3.14 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 46. I/O static characteristics Symbol Parameter Standard IO input low level voltage V IL (1) IO ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 39. Standard I/O input characteristics - CMOS port Figure 40. Standard I/O input characteristics - TTL port Doc ID 14610 Rev 8 Electrical characteristics 81/112 ...
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Electrical characteristics Figure 41 tolerant I/O input characteristics - CMOS port Figure 42 tolerant I/O input characteristics - TTL port Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, ...
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STM32F101xC, STM32F101xD, STM32F101xE Output voltage levels Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol Output Low level voltage for an ...
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Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 48, respectively. Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 10. Table 48. I/O AC characteristics MODEx ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 43. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved ≤ 2/3)T and if the duty cycle is (45-55%) 5.3.15 NRST pin characteristics The NRST ...
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Electrical characteristics 5.3.16 TIM timer characteristics The parameters given in Refer to Section 5.3.13: I/O current injection characteristics alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. TIMx Symbol t Timer resolution time res(TIM) Timer external ...
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STM32F101xC, STM32F101xD, STM32F101xE 2 Table 51 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time ...
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Electrical characteristics 2 Figure 45 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 52. SCL frequency ( External pull-up resistance For speeds around 200 ...
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STM32F101xC, STM32F101xD, STM32F101xE SPI interface characteristics Unless otherwise specified, the parameters given in performed under ambient temperature, f summarized in Table Refer to Section 5.3.13: I/O current injection characteristics input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 53. STM32F10xxx ...
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Electrical characteristics Table 54. SPI characteristics Symbol f SCK SPI clock frequency 1/t c(SCK) t SPI clock rise and fall r(SCK) t time f(SCK) SPI slave input clock duty DuCy(SCK) cycle (1) t NSS setup time su(NSS) (1) t NSS ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 46. SPI timing diagram - slave mode and CPHA=0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure 47. ...
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Electrical characteristics Figure 48. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V 5.3.18 ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 55. ADC characteristics Symbol V Power supply DDA V Positive reference voltage REF+ Current on the V I VREF pin f ADC clock frequency ADC (2) Sampling rate f S (2) f External trigger frequency TRIG ...
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Electrical characteristics The formula above allowed for an error below 1/4 of LSB. Here (from 12-bit resolution). Table 56. R AIN T (cycles) s 1.5 7.5 13.5 28.5 41.5 55.5 71.5 239.5 1. Guaranteed by design, not ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 58. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could ...
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Electrical characteristics Figure 50. Typical connection diagram using the ADC V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly 7 pF). ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 52. Power supply and reference decoupling ( and V REF+ REF- 5.3.19 DAC electrical specifications Table 59. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA ...
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Electrical characteristics Table 59. DAC characteristics (continued) Symbol Parameter DAC DC current consumption I in quiescent mode (Standby DDVREF+ mode) DAC DC current consumption I in quiescent mode (Standby DDA mode) Differential non linearity (1) DNL Difference between two consecutive ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 53. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The ...
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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 54. LQFP144 mm, 144-pin thin quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to ...
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Package characteristics Figure 56. LQFP100 – mm, 100-pin low-profile quad flat package outline 100 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in ...
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STM32F101xC, STM32F101xD, STM32F101xE Figure 58. LQFP64 – mm, 64 pin low-profile quad flat package outline Pin 1 identification Drawing is not to scale. 2. Dimensions ...
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Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 10: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: ● T max is the maximum ambient temperature in °C, A Θ ...
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STM32F101xC, STM32F101xD, STM32F101xE 6.2.2 Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Each temperature range suffix corresponds to a specific guaranteed ambient temperature at ...
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Part numbering 7 Part numbering Table 65. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count pins V = 100 pins Z ...
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STM32F101xC, STM32F101xD, STM32F101xE 8 Revision history Table 66. Document revision history Date Revision 07-Apr-2008 22-May-2008 21-Jul-2008 1 Initial release. Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and the family modified. Small text changes. Note 1 ...
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Revision history Table 66. Document revision history (continued) Date Revision 12-Dec-2008 108/112 STM32F101xC, STM32F101xD, STM32F101xE General-purpose timers (TIMx) on page 19 STM32F101xx family updated to show the low-density family. Table 4: Timer feature comparison Figure 1: STM32F101xC, STM32F101xD and STM32F101xE ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 66. Document revision history (continued) Date Revision 30-Mar-2009 I/O information clarified on cover page. Number of ADC peripherals corrected in Table 2: STM32F101xC, STM32F101xD and STM32F101xE features and peripheral In Table 5: High-density STM32F101xx pin – ...
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Revision history Table 66. Document revision history (continued) Date Revision 21-Jul-2009 110/112 STM32F101xC, STM32F101xD, STM32F101xE Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access line block diagram modified. Note 5 updated and Note 4 STM32F101xx pin definitions. V and T added to ...
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STM32F101xC, STM32F101xD, STM32F101xE Table 66. Document revision history (continued) Date Revision 24-Sep-2009 19-Apr-2011 Number of DACs corrected in I updated in Table 17: Typical and maximum current DD_VBAT consumptions in Stop and Standby Figure 13: Typical current consumption on VBAT ...
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