STM32W108CC STMicroelectronics, STM32W108CC Datasheet
STM32W108CC
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STM32W108CC Summary of contents
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... RX sensitivity; configurable to -100 dBm (1% PER, 20 byte packet) – normal mode output power; configurable dBm March 2012 This is information on a product in full production. STM32W108HB STM32W108CC STM32W108CB STM32W108CZ to 256 Kbytes of embedded Flash memory VFQFPN48 ( mm serial – ...
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... Random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 Power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 6.1.2 2/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARM® Cortex™-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . . 33 Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Externally regulated power ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 6.2.2 6.2.3 6.2.4 6.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.4 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5.1 6.5.2 6.5.3 6.5.4 6.6 Security accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7 Integrated voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8 General-purpose input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 High-frequency internal RC oscillator (OSCHF High-frequency crystal oscillator (OSC24M Low-frequency internal RC oscillator (OSCRC Low-frequency crystal oscillator (OSC32K) ...
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... Universal asynchronous receiver / transmitter (UART 9.6.1 9.6.2 4/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Port x configuration register (Low) (GPIO_PxCFGL Port x configuration register (High) (GPIO_PxCFGH Port x input data register (GPIO_PxIN Port x output data register (GPIO_PxOUT Port x output clear register (GPIO_PxCLR Port x output set register (GPIO_PxSET Port x wakeup monitor register (GPIO_PxWAKE GPIO wakeup filtering register (GPIO_WAKEFILT) ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.6.3 9.6.4 9.6.5 9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.8 Serial controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.8.1 9.8.2 9.8.3 9.8.4 9.9 SPI master mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.10 SPI slave mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.11 Inter-integrated circuit (I2C) interface registers . . . . . . . . . . . . . . . . . . . 100 9.11.1 9.11.2 9.11.3 9.12 Universal asynchronous receiver / transmitter (UART) registers . . . . . . 102 9.12.1 9.12.2 9.12.3 9.12.4 9.13 DMA channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9.13.1 9.13.2 9.13.3 9.13.4 9.13.5 9.13.6 9.13.7 9.13.8 9.13.9 9.13.10 Receive DMA end address register A (SCx_RXENDA 111 RTS/CTS flow control ...
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... Timer x auto-reload register (TIMx_ARR 165 10.3.11 Timer x capture/compare 1 register (TIMx_CCR1 166 6/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 PWM mode ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.3.12 Timer x capture/compare 2 register (TIMx_CCR2 166 10.3.13 Timer x capture/compare 3 register (TIMx_CCR3 167 10.3.14 Timer x capture/compare 4 register (TIMx_CCR4 167 10.3.15 Timer 1 option register (TIM1_OR 168 10.3.16 Timer 2 option register (TIM2_OR 169 10.3.17 Timer x interrupt configuration register (INT_TIMxCFG 170 10.3.18 Timer x interrupt flag register (INT_TIMxFLAG 170 10 ...
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... Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 219 14.9 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 14.9.1 8/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Top-level set interrupts configuration register (INT_CFGSET 193 Top-level clear interrupts configuration register (INT_CFGCLR 194 Top-level set interrupts pending register (INT_PENDSET 195 Top-level clear interrupts pending register (INT_PENDCLR 196 Top-level active interrupts register (INT_ACTIVE) ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 14.9.2 14.9.3 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Doc ID 16252 Rev 13 Contents 9/232 ...
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... To maintain the strict timing requirements imposed by the ZigBee and IEEE 802.15.4-2003 standards, the STM32W108 integrates a number of MAC functions into the hardware. The MAC hardware handles automatic ACK transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well as automatic filtering of 10/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ PA SYNTH DAC PA ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ received packets. A packet trace interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the STM32W108. The STM32W108 offers a number of advanced power management features that enable long battery life. A high-frequency internal RC oscillator allows the processor core to begin code execution quickly upon waking. Various deep sleep modes are available with less than 1 µ ...
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... RC oscillator. Alternatively, all clocks can be disabled for the lowest power mode. In the lowest power mode, only external events on 12/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 2 C (master-only), or UART operation, and the Serial Doc ID 16252 Rev (master-only) operation ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ GPIO pins will wake up the chip. The STM32W108 has a fast startup time (typically 100 µs) from deep sleep to the execution of the first ARM® Cortex-M3 instruction. The STM32W108 contains three power domains. The always-on high voltage supply powers the GPIO pads and critical chip functions ...
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... The conditions under which the hardware (core) sets or clears this field are explained in details in the bitfield description, as well as the events that may be generated by writing to the bit. 14/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Description Software can read and write to these bits. Software can only read these bits. ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 3 Pinout and pin description Figure 2. 48-pin VFQFPN pinout VDD_24MHZ VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF BIAS_R VDD_PADSA PC5, TX_ACTIVE nRESET Ground pad on back ...
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... RF_N 5 4 VDD_RF 6 5 RF_TX_ALT_P 7 6 RF_TX_ALT_N 8 7 VDD_IF 9 8 BIAS_R 16/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Ground pad on back Direction Power 1.8V high-frequency oscillator supply Power 1.8V VCO supply ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no VDD_PADSA PC5 11 10 TX_ACTIVE 12 11 nRESET PC6 OSC32B 13 nTX_ACTIVE PC7 14 OSC32A OSC32_EXT 15 12 VREG_OUT 16 13 VDD_PADS 17 14 VDD_CORE PA7 18 TIM1_CH4 REG_EN Direction Power Analog pad supply (1.8V) ...
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... SC1SCLK PB4 TIM2_CH4 (see also Pin 24 UART_RTS SC1nSSEL 18/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Direction I/O Digital I/O Timer 2 channel 3 output Enable remap with TIM2_OR[6] O Enable timer output in TIM2_CCER Select alternate output function with GPIO_PBCFGL[15:12] I Timer 2 channel 3 input. Enable remap with TIM2_OR[6]. UART CTS handshake of Serial Controller 1 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA0 TIM2_CH1 (see also Pin 30 SC2MOSI PA1 TIM2_CH3 (see also Pin 19) SC2SDA 22 18 SC2MISO 23 19 VDD_PADS Direction I/O Digital I/O Timer 2 channel 1 output Disable remap with TIM2_OR[4] ...
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... SC2nSSEL TRACECLK (see also Pin 25 21 36) TIM2_CH2 (see also Pin 31) 20/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Direction I/O Digital I/O Timer 2 channel 4 output Disable remap with TIM2_OR[7] O Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[11:8] I Timer 2 channel 4 input. Disable remap with TIM2_OR[7]. ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA4 ADC4 PTI_EN 26 22 TRACEDATA2 PA5 ADC5 PTI_DATA 27 23 nBOOTMODE TRACEDATA3 28 24 VDD_PADS PA6 29 TIM1_CH3 Direction I/O Digital I/O ADC Input 4. Select analog function with Analog GPIO_PACFGH[3:0]. Frame signal of Packet Trace Interface (PTI). ...
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... SC1MISO SC1MOSI 30 25 SC1SDA SC1TXD TIM2_CH1 (see also Pin 21) 22/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Direction I/O Digital I/O SPI slave data out of Serial Controller 1 Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[4] O Select SPI with SC1_MODE Select slave with SC1_SPICR Select alternate output function with GPIO_PBCFGL[7:4] ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB2 SC1MISO SC1MOSI 31 26 SC1SCL SC1RXD TIM2_CH2 (see also Pin 25) SWCLK 32 27 JTCK PC2 JTDO 33 28 SWO Direction I/O Digital I/O SPI master data in of Serial Controller 1 I Select SPI with SC1_MODE ...
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... IRQA TRACECLK (see also Pin 25) TIM1CLK TIM2MSK 37 VDD_PADS 24/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Direction Digital I/O I/O Either Enable with GPIO_DBGCFG[5], or enable Serial Wire mode (see JTMS description) JTAG data in from debugger Selected when in JTAG mode (default mode, see JTMS I description, Pin 35) ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PC1 ADC3 SWO (see also Pin 38 31 33) TRACEDATA0 39 32 VDD_MEM PC0 JRST 40 33 (1) IRQD TRACEDATA1 PB7 ADC2 41 34 (1) IRQC TIM1_CH2 Direction I/O Digital I/O ADC Input 3 Analog Enable analog function with GPIO_PCCFGL[7:4] ...
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... OSCB 48 39 OSCA 49 41 GND 1. IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and GPIO_IRQDSEL registers. 26/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Direction I/O Digital I/O High current ADC Input 1 Analog Enable analog function with GPIO_PBCFGH[11:8] I External interrupt source B ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 4 Embedded memory Figure 4. STM32W108xB memory mapping 0xE00FFFFF 0xE00FF000 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE0003000 0xE0002000 0xE0001000 0xE0000000 0x42002XXX 0x42000000 0x40000XXX 0x40000000 0x22002000 0x22000000 0x20001FFF 0x20000000 0x080409FF Customer Info Block (0.5kB) 0x08040800 0x080407FF 0x08040000 0x0801FFFF Main Flash Block (128kB) ...
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... Embedded memory Figure 5. STM32W108CC and STM32W108CZ memory mapping 28/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 4.1 Flash memory The STM32W108 provides Flash memory in four separate blocks as follows: ● Main Flash Block (MFB) ● Fixed Information Block (FIB) ● Fixed Information Block Extension (FIB-EXT) ● Customer Information Block (CIB) The size of these blocks and associated page size is described in Table 3 ...
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... Each bit in the map represents a 32-byte block of RAM for STM32W108xB and 64 bytes of RAM for STM32W108CC and STM32W108CZ. When the bit is set the block is write protected. The fine granularity RAM memory protection mechanism is also available to the peripheral DMA controllers ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 4.3 Memory protection unit The STM32W108 includes the ARM® Cortex-M3 Memory Protection Unit, or MPU. The MPU controls access rights and characteristics eight address regions, each of which may be divided into eight equal sub-regions. Refer to the ARM® Cortex-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU ...
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... The STM32W108 Tx path produces an O-QPSK-modulated signal using the analog front end and digital baseband. The area- and power-efficient Tx architecture uses a two-point modulation scheme to modulate the RF signal generated by the synthesizer. The modulated RF signal is fed to the integrated PA and then out of the STM32W108. 32/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ diagram. Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 5.2.1 Tx baseband The STM32W108 Tx baseband in the digital domain spreads the 4-bit symbol into its IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to calibrate the Tx module to reduce silicon process, temperature, and voltage variations. 5.2.2 TX_ACTIVE and nTX_ACTIVE signals For applications requiring an external PA, two signals are provided called TX_ACTIVE and nTX_ACTIVE ...
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... Thermal noise in the analog circuitry is digitized to provide entropy for a true random number generator (TRNG). The TRNG produces 16-bit uniformly distributed numbers. The Software can use the TRNG to seed a pseudo random number generator (PNRG). The TRNG is also used directly for cryptographic key generation. 34/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6 System modules System modules encompass power, resets, clocks, system timers, power management, and encryption. Figure 6 Figure 6. System module block diagram recomended connections for internal regulator External Regulator optional connections for external regulator shows these modules and how they interact. ...
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... When using an external regulator, the VREG_1V8 regulator output pin (VREG_OUT) must be left unconnected. When using an external regulator, this external nominal 1.8 V supply has to be connected to both VDD_CORE pins and to the VDD_MEM, VDD_PADSA, VDD_VCO, VDD_RF, VDD_IF, VDD_PRE and VDD_SYNTH pins. 36/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 56. 60). Doc ID 16252 Rev 13 Section 7: Integrated voltage Section 8.1.3: ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.2 Resets The STM32W108 resets are generated from a number of sources. Each of these reset sources feeds into central reset detection logic that causes various parts of the system to be reset depending on the state of the system and the nature of the reset event. ...
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... We recommend that in a live application (i.e. no debugger attached) the watchdog be enabled by default so that the STM32W108 can be restarted. 38/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Always-on domain power supply failure Core or memory domain power supply failure NRST pin asserted Watchdog timer expired Software reset by SYSERSETREQ from ARM® ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.2.3 Reset generation The Reset Generation module responds to reset sources and generates the following reset signals: ● PORESET ● SYSRESET ● DAPRESET ● PRESETHV ● PRESETLV Table 4 shows which reset sources generate certain resets. Table 4. Generated resets Reset source ...
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... RSTB_PIN: When set to ‘1’, the reset is due to an external reset pin signal. Bit 1 POWER_LV: When set to ‘1’, the reset is due to the application of a Core power supply (or previously failed). Bit 0 POWER_HV: Always set to ‘1’, Normal power applied 40/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.3 Clocks The STM32W108 integrates four oscillators: ● High frequency RC oscillator ● 24 MHz crystal oscillator ● 10 kHz RC oscillator ● 32.768 kHz crystal oscillator Figure 7 shows a block diagram of the clocks in the STM32W108. This simplified view shows all the clock sources and the general areas of the chip to which they are routed. ...
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... A low-frequency 32.768 kHz crystal oscillator (OSC32K) is provided as an optional timing reference for on-chip timers. This oscillator is designed for use with an external watch crystal. See also Section 14.5.4: Low frequency external clock characteristics on page 42/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 211. 211. 212. 212. ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.3.5 Clock switching The STM32W108 has two switching mechanisms for the main system clock, providing four clock modes. The register bit OSC24M_SEL in the OSC24M_CTRL register switches between the high- frequency RC oscillator (OSCHF) and the high-frequency crystal oscillator (OSC24M) as the main system clock (SCLK) ...
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... To enable the watchdog timer the application must first write the enable code 0xEABE to the WDOG_CTRL register and then set the WDOG_EN register bit. To disable the timer the application must write the disable code 0xDEAD to the WDOG_CTRL register and then set the WDOG_DIS register bit. 44/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.4.2 Sleep timer The STM32W108 integrates a 32-bit timer dedicated to system timing and waking from sleep at specific times. The sleep timer can use either the calibrated 1 kHz reference(CLK1K), or the 32 kHz crystal clock (CLK32K). The default clock source is the internal 1 kHz clock. The sleep timer clock source is chosen with the SLEEPTMR_CLKSEL register ...
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... Watchdog restart register (WDOG_RESTART) Write any value to this register to kick-start the watchdog. Address: Reset value: Sleep timer configuration register (SLEEPTMR_CFG) This register sets the various options for the Sleep timer. Address: Reset value: 46/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 11. Sleep timer configuration register (SLEEPTMR_CFG SLEEP SLEEP TMR_ TMR_ Reserved REVER ENABL Bit 12 SLEEPTMR_REVERSE: 0: count forward; 1: count backwards. Only changes when ENABLE bit is set to ‘0’. Bit 11 SLEEPTMR_ENABLE: 0: disable sleep timer; 1: enable sleep timer. ...
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... Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’. If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated. Therefore it is recommended to disable interrupts before changing this register. 48/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x4000 6014 0x0000 0000 26 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Sleep timer compare A low register (SLEEPTMR_CMPAL) Address: Reset value: Table 15. Sleep timer compare A low register (SLEEPTMR_CMPAL Bits [15:0] SLEEPTMR_CMPAL_FIELD: Sleep timer compare A low value [15:0]. Writing to this register puts value in hold register until a write to the SLEEPTMR_CMPAH register. Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘ ...
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... Note: Bits are cleared when set to ‘1’. Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A Note: Bits are cleared when set to ‘1’. Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow Note: Bits are cleared when set to ‘1’. 50/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x4000 6024 0x0000 FFFF Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Sleep timer interrupt mask register (INT_SLEEPTMRCFG) Address: 0x4000 A054 Reset value: Table 19. Sleep timer interrupt mask register (INT_SLEEPTMRCFG Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow Sleep timer clock source enables (SLEEPTMR_CLKEN) This timer controls the low power clock gated modes ...
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... The Wakeup Recording module monitors all possible wakeup sources. More than one wakeup source may be recorded because events are continually being recorded (not just in deep-sleep), since another event may happen between the first wake event and when the STM32W108 wakes up. 52/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 6.5.2 Basic sleep modes The power management state diagram in management controller. Figure 8. Power management state diagram DEEP SLEEP PRE- DEEP SLEEP CSYSPWRUPREQ & INHIBIT Figure 8 shows the basic operation of the power CDBGPWRUPREQ set CDBGPWRUPREQ cleared Deep sleep requested ...
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... SWJ indicates that a debugger wants to access memory actively in the STM32W108. Therefore, whenever the CSYSPWRUPREQ bit is set while the STM32W108 is awake, the STM32W108 cannot enter deep sleep until this bit is cleared. This ensures the STM32W108 does not disrupt debug communication into memory. 54/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Clearing both CSYSPWRUPREQ and CDBGPWRUPREQ allows the STM32W108 to achieve a true deep sleep state (deep sleep 1 or 2). Both of these signals also operate as wake sources, so that when a debugger connects to the STM32W108 and begins accessing the chip, the STM32W108 automatically comes out of deep sleep. When the debugger initiates access while the STM32W108 is in deep sleep, the SWJ intelligently holds off the debugger for a brief period of time until the STM32W108 is properly powered and ready ...
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... No load current 1V8 regulator current limit 1V25 regulator current limit 56/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Min. Typ. Max. 2.1 3.6 -5% 1.8 +5% -5% 1 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 21. 1.8 V integrated voltage regulator specifications (continued) Parameter 1V8 regulator start-up time 1V25 regulator start-up time An external 1.8 V regulator may replace both internal regulators. The STM32W108 can control external regulators during deep sleep using open-drain GPIO PA7, as described in ...
Page 58
... Only one device at a time can control a GPIO output. The output is controlled in normal output mode by the GPIO_PxOUT register and in alternate output mode by a peripheral device. When in input mode or analog mode, digital output is disabled. 58/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ VDD_PADS P-MOS Output control ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 8.1 Functional description 8.1.1 GPIO ports The 24 GPIO pins are grouped into three ports: PA, PB, and PC. Individual GPIOs within a port are numbered according to their bit positions within the GPIO registers. Note: Because GPIO port registers' functions are identical, the notation Px is used here to refer to PA, PB ...
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... The DEBUG_DIS bit in the GPIO_DBGCFG register can disable the Serial Wire/JTAG debugger interface. When this bit is set, all debugger-related pins (PC0, PC2, PC3, PC4) behave as standard GPIO. 60/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ GPIO_PxCFGH/L Open-drain output. An onboard peripheral controls 0xD the output pull up is required, it must be external ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 24. GPIO forced functions GPIO GPIO_EXTREGEN bit set in the PA7 GPIO_DBGCFG register PC0 Debugger interface is active in JTAG mode PC2 Debugger interface is active in JTAG mode PC3 Debugger interface is active in JTAG mode PC4 Debugger interface is active in JTAG mode Debugger interface is active in Serial Wire ...
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... GPIO_PxOUT register controls the output. The GPIO_PxSET and GPIO_PxCLR registers can atomically set and clear bits within GPIO_PxOUT register. These set and clear registers simplify software using the output port because they eliminate the need to disable interrupts to perform an atomic read-modify-write operation of GPIO_PxOUT. 62/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ When configured in output mode: ● The output drivers are enabled and are controlled by the value written to GPIO_PxOUT: ● In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the pin. ● In push-pull mode: 0 activates the N-MOS current sink; 1 activates the P-MOS current source. ● ...
Page 64
... GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively. Table 25 shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the GPIO pin used for the external interrupt. 64/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 for information on the STM32W108's ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 25. IRQC/D GPIO selection GPIO_IRQxSEL some cases, it may be useful to assign IRQC or IRQD to an input also in use by a peripheral, for example to generate an interrupt from the slave select signal (nSSEL SPI slave mode interface. ...
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... Alternate signal assignment (remapped). 5. Overrides in JTAG mode as an input with pull up. 6. Overrides in JTAG mode as a push-pull output. 7. Overrides in Serial Wire mode as either a push-pull output floating input, controlled by the debugger. 66/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Analog Alternate function PTI_DATA, ADC5 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 8.5 General-purpose input / output (GPIO) registers 8.5.1 Port x configuration register (Low) ( Address offset: 0xB000 (GPIO_PACFGL), 0xB400 (GPIO_PBCFGL) and 0xB800 (GPIO_PCCFGL) Reset value: Table 27. Port x configuration register (Low Px3_CFG rw Bits [15:12] Px3_CFG: GPIO configuration control. 0x0: Analog, input or output (GPIO_PxIN always reads 1). ...
Page 68
... Bit 4 Px4: Input level at pin Px4. Bit 3 Px3: Input level at pin Px3. Bit 2 Px2: Input level at pin Px2. Bit 1 Px1: Input level at pin Px1. Bit 0 Px0: Input level at pin Px0. 68/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 8.5.4 Port x output data register (GPIO_PxOUT) Address offset: 0xB00C (GPIO_PAOUT), 0xB40C (GPIO_PBOUT) Reset value: Table 30. Port x output data register (GPIO_PxOUT Reserved Bit 7 Px7: Output data for Px7. Bit 6 Px6: Output data for Px6. ...
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... Px2: Write 1 to set the output data bit for Px2 (writing 0 has no effect). Bit 1 Px1: Write 1 to set the output data bit for Px1 (writing 0 has no effect). Bit 0 Px0: Write 1 to set the output data bit for Px0 (writing 0 has no effect). 70/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ and 0xB810 (GPIO_PCSET) 0x0000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 8.5.7 Port x wakeup monitor register (GPIO_PxWAKE) Address offset: 0xBC08 (GPIO_PAWAKE), 0xBC0C (GPIO_PBWAKE) Reset value: Table 33. Port x wakeup monitor register (GPIO_PxWAKE Reserved Bit 7 Px7: Write 1 to enable wakeup monitoring of Px7. Bit 6 Px6: Write 1 to enable wakeup monitoring of Px6. ...
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... PA2. 0x03: PA3. 0x04: PA4. 0x05: PA5. 0x06: PA6. 0x07: PA7. 0x08: PB0. 0x09: PB1. 0x0A: PB2. 0x0B: PB3. 0x0C: PB4. 72/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 000F (GPIO_IRQCSEL) and 0x0000 0010 (GPIO_IRQDSEL Reserved Reserved Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 8.5.10 GPIO interrupt x configuration register (GPIO_INTCFGx) Address offset: 0xA860 (GPIO_INTCFGA), 0xA864 (GPIO_INTCFGB), Reset value: Table 36. GPIO interrupt x configuration register (GPIO_INTCFGx Reserved Bit [8] GPIO_INTFILT: Set this bit to enable digital filtering on IRQx. Bits [7:5] GPIO_INTMOD: IRQx triggering mode. ...
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... Bit 4 GPIO_EXTREGEN: : Disable REG_EN override of PA7's normal GPIO configuration. 0: Enable override. 1: Disable override. Bit 3 Reserved: this bit can change during normal operation. When writing to GPIO_DBGCFG, the value of this bit must be preserved. 74/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0010 Reserved 10 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 8.5.13 GPIO debug status register (GPIO_DBGSTAT) Address offset: 0xBC04 Reset value: Table 39. GPIO debug status register (GPIO_DBGSTAT Bit 3 GPIO_BOOTMODE: The state of the nBOOTMODE signal sampled at the end of reset. 0: nBOOTMODE was not asserted (it read high). ...
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... Note: The notation SCx means that either SC1 or SC2 may be substituted to form the name of a specific register or field within a register. 76/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 Figure 10 shows ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure 10. Serial controller block diagram SCx Interrupt SCx_MODE SCx TX DMA channel SCx RX DMA channel 9.2 Configuration Before using a serial controller, it should be configured and initialized as follows: 1. Set up the parameters specific to the operating mode (master/slave for SPI, baud rate for UART, etc.). ...
Page 78
... SCLK (Serial Clock) - outputs the serial clock used by MOSI and MISO The GPIO pins used for these signals are shown in needed to drive the nSSEL signals on slave devices. 78/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ PB1 PB2 SC1MISO input SC1MOSI input SC1SCL alternate ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 42. SPI master GPIO usage Parameter Direction GPIO configuration SC1 pin SC2 pin 9.3.1 Setup and configuration Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is enabled by the following register settings: ● The serial controller mode register (SCx_MODE) is ‘2’. ...
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... MOSI pin sets the SC_SPITXFREE bit in the SCx_SPISTAT register. When the transmit FIFO empties and the last character has been shifted out, the SC_SPITXIDLE bit in the SCx_SPISTAT register is set. 80/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Frame formats SCLK out MOSI ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Characters received are stored in the receive FIFO. Receiving characters sets the SC_SPIRXVAL bit in the SCx_SPISTAT register, indicating that characters can be read from the receive FIFO. Characters received while the receive FIFO is full are dropped, and the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error condition until the receive FIFO is drained ...
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... The SPI slave controller supports various frame formats depending upon the clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8 6). The SC_SPIPOL, SC_SPIPHA, and SC_SPIORD bits are defined within the SCx_SPICFG registers. 82/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ MOSI MISO Input Output ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 45. SPI slave mode formats SCx_SPICFG (1) SC_SPIxxx MST ORD PHA POL nSSEL SCLK MOSI in MISO out SCLK MOSI in MISO out nSSEL SCLK MOSI in MISO out nSSEL SCLK MOSI in MISO ...
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... Subsequent rising edges set a status bit but are otherwise ignored. The 3-bit field SC_RXSSEL in the SCx_DMASTAT register records what, if anything, was saved to the SCx_RXCNTSAVED register, and whether or not another rising edge occurred on nSSEL. 84/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.4.4 Interrupts SPI slave controller second level interrupts are generated on the following events: ● Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the transition or the high level of SC_SPITXIDLE) ● Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the transition or the high level of SC_SPITXFREE) ● ...
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... SCL timing, the clock rate must be lowered to 375 kbps. 9.5.2 Constructing frames 2 The I C master controller supports generating various frame segments by means of the SC_TWISTART, SC_TWISTOP, SC_TWISEND, and SC_TWIRECV bits in the SCx_TWICTRL1 registers. 86/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 12MHz ---------------------------------------- - Rate = ( LIN I2C clock rate programming on page 86 2 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 2 Table 48 master frame segments SCx_TWICTRL1 (1) SC_TWIxxxx START SEND RECV STOP The notation xxx means that the corresponding column header below is inserted to form the field name. ...
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... SCx_DATA register. Alternatively, the SC_TWIRXFIN bit in the SCx_TWISTAT register can be used for waiting. Now the SC_TWIRXNAK bit in the SCx_TWISTAT register indicates if a NACK or ACK was received from an I 88/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure IDLE START Segment ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.5.3 Interrupts master controller interrupts are generated on the following events: ● Bus command (SC_TWISTART/SC_TWISTOP) completed ( transition of SC_TWICMDFIN) ● Character transmitted and slave device responded with NACK ● Character transmitted ( transition of SC_TWITXFIN) ● Character received ( transition of SC_TWIRXFIN) ● ...
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... If this bit is clear, the parity bit is even, and if set, the parity bit is odd. Even parity is the exclusive-or of all of the data bits, and odd parity is the inverse of the even parity value. SC1_UARTODD has no effect if SC1_UARTPAR is clear. 90/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 24 MHz = ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ A UART character frame contains, in sequence: ● The start bit ● The least significant data bit ● The remaining data bits ● If parity is enabled, the parity bit ● The stop bit, or bits stop bits are selected. Figure 12 shows the UART character frame format, with optional bits indicated ...
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... TXD, RXD nCTS, nRTS 1. The notation xxx means that the corresponding column header below is inserted to form the field name. 92/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ STM32W108 RXD UART Receiver nRTS TXD nCTS No RTS/CTS flow control Flow control using RTS/CTS with software control of nRTS: ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.6.4 DMA The DMA Channels section describes how to configure and use the serial receive and transmit DMA channels. The receive DMA channel has special provisions to record UART receive errors. When the DMA channel transfers a character from the receive FIFO to a buffer in memory, it checks the stored parity and frame error status flags ...
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... Serial controller DMA channels include additional features specific to the SPI and UART operation and are described in those sections. 94/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.8 Serial controller registers 9.8.1 Serial mode register (SCx_MODE) Address offset: 0xC854 (SC1_MODE) and 0xC054 (SC2_MODE) Reset value: Table 52. Serial mode register (SCx_MODE Bits [1:0] SC_MODE: Serial controller mode. 0: Disabled. 1: UART mode (valid only for SC1). ...
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... INT_SCTXUND: Transmit buffer underrun interrupt enable. Bit 3 INT_SCRXOVF: Receive buffer overrun interrupt enable. Bit 2 INT_SCTXIDLE: Transmitter idle interrupt enable. Bit 1 INT_SCTXFREE: Transmit buffer free interrupt enable. INT_SCRXVAL: Receive buffer has data interrupt enable. Bit 0 96/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.8.4 Serial controller interrupt mode register (SCx_INTMODE) Address offset: 0xA854 (SC1_INTMODE) and 0xA858 (SC2_INTMODE) Reset value: Table 55. Serial controller interrupt mode register (SCx_INTMODE Bit 2 SC_TXIDLELEVEL: Transmitter idle interrupt mode 0: Edge triggered Bit 1 SC_TXFREELEVEL: Transmit buffer free interrupt mode ...
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... SC_SPIPHA: Clock phase configuration: clear this bit to sample on the leading (first edge) and set this bit to sample on the second edge. Bit 0 SC_SPIPOL: Clock polarity configuration: clear this bit for a rising leading edge and set this bit for a falling leading edge. 98/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.9.3 SPI status register (SCx_SPISTAT) Address offset: 0xC840 (SC1_SPISTAT) and 0xC040 (SC2_SPISTAT) Reset value: Table 58. SPI status register (SCx_SPISTAT Bit 3 SC_SPITXIDLE: This bit is set when both the transmit FIFO and the transmit serializer are empty ...
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... SC_TWIRXFIN: This bit is set when a byte is received. It clears on the next I Bit 1 SC_TWITXFIN: This bit is set when a byte is transmitted. It clears on the next I Bit 0 SC_TWIRXNAK: This bit is set when a NACK is received from the slave. It clears on the next bus activity. 100/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved 10 9 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 2 9.11 control 1 register (SCx_TWICTRL1) Address offset: 0xC84C (SC1_TWICTRL1) and 0xC04C (SC2_TWICTRL1) Reset value: 2 Table 62 control 1 register (SCx_TWICTRL1 Bit 3 SC_TWISTOP: Setting this bit sends the STOP command. It clears when the command completes. ...
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... SC_UARTTXFREE: This bit is set when the transmit FIFO has space for at least one byte. Bit 1 SC_UARTRXVAL: This bit is set when the receive FIFO contains at least one byte. Bit 0 SC_UARTCTS: This bit is set when both the transmit FIFO and the transmit serializer are empty. 102/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0040 Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.12.2 UART configuration register (SC1_UARTCFG) Address offset: 0xC85C Reset value: Table 65. UART configuration register (SC1_UARTCFG Reserved Bit 6 SC_UARTAUTO: Set this bit to enable automatic nRTS control by hardware (SC_UARTFLOW must also be set). When automatic control is enabled, nRTS will be deasserted when the ...
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... UART baud rate fractional period register (SC1_UARTFRAC Bits [0] SC_UARTFRAC: The fractional part of the baud rate period (F) in the equation: Rate = 24 MHz / ( ( 104/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved SC_UARTPER rw 0x0000 0000 26 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.13 DMA channel registers 9.13.1 Serial DMA control register (SCx_DMACTRL) Address offset: 0xC830 (SC1_DMACTRL) and 0xC030 (SC2_DMACTRL) Reset value: Table 68. Serial DMA control register (SCx_DMACTRL Reserved Bit 5 SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears automatically. ...
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... Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and when the receive DMA is reset. Bit 3 This bit is set when DMA transmit buffer B is active. 106/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Bit 2 This bit is set when DMA transmit buffer A is active. Bit 1 This bit is set when DMA receive buffer B is active. Bit 0 This bit is set when DMA receive buffer A is active. 9.13.3 Transmit DMA begin address register A (SCx_TXBEGA) Address offset: 0xC810 (SC1_TXBEGA) and 0xC010 (SC2_TXBEGA) Reset value: Table 70 ...
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... Transmit DMA end address register B (SCx_TXENDB Reserved Bits [13:0] SC_TXENDB: Address of the last byte that will be read from the DMA transmit buffer B. 108/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x2000 0000 Reserved SC_TXENDA rw 0x2000 0000 26 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.13.7 Transmit DMA count register (SCx_TXCNT) Address offset: 0xC828 (SC1_TXCNT) and 0xC028 (SC2_TXCNT) Reset value: Table 74. Transmit DMA count register (SCx_TXCNT Reserved Bits [13:0] SC_TXCNT: The offset from the start of the active DMA transmit buffer from which the next byte will be read ...
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... Address offset: 0xC808 (SC1_RXBEGB) and 0xC008 (SC2_RXBEGB) Reset value: Table 76. Receive DMA begin address register B (SCx_RXBEGB Reserved Bits [13:0] SC_RXBEGB: DMA receive buffer B start address. 110/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x2000 0000 Reserved SC_RXBEGA rw 0x2000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.13.10 Receive DMA end address register A (SCx_RXENDA) Address offset: 0xC804 (SC1_RXENDA) and 0xC004 (SC2_RXENDA) Reset value: Table 77. Receive DMA end address register A (SCx_RXENDA Reserved Bits [13:0] SC_RXENDA: Address of the last byte that will be written in the DMA receive buffer A. ...
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... SC_RXCNTB: The offset from the start of DMA receive buffer B at which the next byte will be written. This register is set to zero when the buffer is loaded and when the DMA is reset. If this register is written when the buffer is not loaded, the buffer is loaded. 112/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 26 25 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 9.13.14 Saved receive DMA count register (SCx_RXCNTSAVED) Address offset: 0xC870 (SC1_RXCNTSAVED) and 0xC070 (SC2_RXCNTSAVED) Reset value: Table 81. Saved receive DMA count register (SCx_RXCNTSAVED Reserved Bits [13:0] SC_RXCNTSAVED: Receive DMA count saved in SPI slave mode when nSSEL deasserts. ...
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... Note that an overflow error occurs at the input to the receive FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. 114/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10 General-purpose timers Each of the STM32W108's two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler ...
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... General-purpose timers Figure 15. General-purpose timer block diagram Note: The internal signals shown in descriptions on page 150 components are interconnected. 116/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure 15 are described in and are used throughout the text to describe how the timer Doc ID 16252 Rev 13 Section 10.1.15: Timer signal ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.1 Functional description The timers can optionally use GPIOs in the PA and PB ports for external inputs or outputs. As with all STM32W108 digital inputs, a GPIO used as a timer input can be shared with other uses of the same pin. Available timer inputs include an external timer clock, a clock mask, and four input channels ...
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... It can be changed on the fly as this control register is buffered. The new prescaler ratio is used starting at the next update event. Figure 16 gives an example of the counter behavior when the prescaler ratio is changed on the fly. Figure 16. Counter timing diagram with prescaler division change from 118/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.1.2 Counter modes Up-counting mode In up-counting mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generated at each counter overflow, by setting the TIM_UG bit in the TIMx_EGR register using the slave mode controller ...
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... General-purpose timers Figure 18. Counter timing diagram, internal clock divided by 4 Figure 19. Counter timing diagram, update event when TIM_ARBE = 0 (TIMx_ARR not buffered) 120/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure 20. Counter timing diagram, update event when TIM_ARBE = 1 (TIMx_ARR buffered) Down-counting mode In down-counting mode, the counter counts from the auto-reload value (contents of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. ...
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... This avoids updating the shadow registers while writing new values in the buffer registers. Then no update event occurs until the TIM_UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. 122/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates an update event, but without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and capture interrupt when clearing the counter on the capture event. ...
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... General-purpose timers Figure 24. Counter timing diagram, update event with TIM_ARBE = 1 (counter underflow) Figure 25. Counter timing diagram, update event with TIM_ARBE = 1 (counter overflow) 124/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.1.3 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (PCLK) ● External clock mode 1: external input pin (TIy) ● External clock mode 2: external trigger input (ETR) ● Internal trigger input (ITR0): using the other timer as prescaler. Refer to the ...
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... When a rising edge occurs on TI2, the counter counts once and the INT_TIMTIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on the TI2 input. Figure 28. Control circuit in External Clock mode 1 126/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ External clock source mode 2 This mode is selected by writing TIM_ECE = 1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The TIM_EXTRIGSEL bits in the TIMx_OR register select a clock signal that drives ETR, as ...
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... Figure 31. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate reference signal, OCyREF, which is only used internally. OCyREF is always active high, but it may be inverted to create the output signal, OCy, that controls a GPIO output. 128/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure 32. Capture/compare channel 1 main circuit Figure 33. Output stage of capture/compare channel (channel 1) The capture/compare block is made of a buffer register and a shadow register. Writes and reads always access the buffer register. In capture mode, captures are first written to the shadow register, then copied into the buffer register ...
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... This sequence avoids missing a capture that could happen after reading the flag and before reading the data. Note: Software can generate IC interrupt requests by setting the corresponding TIM_CCyG bit in the TIMx_EGR register. 130/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.1.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICy signals are mapped on the same TIy input. ● These two ICy signals are active on edges with opposite polarity. ...
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... TIM_CCyP = 0 and TIM_CCyE = 1 to toggle the OCy output pin when TIMx_CNT matches TIMx_CCRy, TIMx_CCRy buffer is not used, OCy is enabled and active high. 5. Enable the counter by setting the TIM_CEN bit in the TIMx_CR1 register. 132/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Section 10.1.8: Output compare mode on page Doc ID 16252 Rev 13 132. ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ To control the output waveform, software can update the TIMx_CCRy register at any time, provided that the buffer register is not enabled (TIM_OCyBE = 0). Otherwise TIMx_CCRy shadow register is updated only at the next update event. An example is given in Figure 35. Output compare mode, toggle on OC1 10 ...
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... TIM_CMS bits configuration. The direction bit (TIM_DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to more information. 134/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 119. Figure 36 for more information. Center-aligned mode (up/down counting) on page 122 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure 37 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR = 8, ● PWM mode is the PWM mode 1, ● The output compare flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for TIM_CMS = 01 in the TIMx_CR1 register. ...
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... A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: In up-counting: TIMx_CNT < TIMx_CCRy ≤ TIMx_ARR (in particular, 0 < TIMx_CCRy), ● ● In down-counting: TIMx_CNT > TIMx_CCRy. 136/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Figure 38. Example of one pulse mode For example, to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a rising edge is detected on the TI2 input pin, using TI2FP2 as trigger 1: ● Map TI2FP2 on TI2 by writing TIM_IC2S = 01 in the TIMx_CCMR1 register. ...
Page 138
... The count direction corresponds to the rotation direction of the connected sensor. summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time. 138/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 Table 86). Table 86 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 86. Counting direction versus encoder signals Level on opposite Active signal (TI1FP1 for edges TI2, TI2FP2 for Counting on TI1 only Counting on TI2 only Counting on TI1 and TI2 An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally used to convert an encoder's differential outputs to digital signals, and this greatly increases noise immunity ...
Page 140
... XOR gate that combines the three input pins TIMxC2 to TIMxC4. The XOR output can be used with all the timer input functions such as trigger or input capture especially useful to interface to Hall effect sensors. 140/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.1.13 Timers and external trigger synchronization The timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode Reset mode reinitializes the counter and its prescaler in response to an event on a trigger input ...
Page 142
... TI1 becomes high. The INT_TIMTIF flag in the INT_TIMxFLAG register is set when the counter starts and when it stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on the TI1 input. Figure 42. Control circuit in Gated mode 142/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Slave mode: Trigger mode In Trigger mode the counter starts in response to an event on a selected input. In the following example, the up-counter starts in response to a rising edge on the TI2 input: ● Configure channel 2 to detect rising edges on TI2 Configure the input filter duration. In this example, no filter is required so TIM_IC2F = 0000 ...
Page 144
... ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. Figure 44. Control circuit in External clock mode 2 + Trigger mode 144/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.1.14 Timer synchronization The two timers can be linked together internally for timer synchronization or chaining. A timer configured in Master mode can reset, start, stop or clock the counter of the other timer configured in Slave mode. Figure 45 presents an overview of the trigger selection and the master mode selection blocks ...
Page 146
... Configure Timer 2 in gated mode (TIM_SMS = 101 in the TIM2_SMCR register). ● Reset Timer 1 by writing 1 in the TIM_UG bit (TIM1_EGR register). 146/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ for connections. Timer 2 counts on the divided internal clock only when Figure 46, the Timer 2 counter and prescaler are not initialized before ...
Page 147
... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ ● Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register). ● Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL). ● Enable Timer 2 by writing 1 in the TIM_CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing 1 in the TIM_CEN bit (TIM1_CR1 register). ...
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... As in the previous example, both counters can be initialized before starting counting. Figure 47 shows the behavior with the same configuration shown in mode instead of gated mode (TIM_SMS = 110 in the TIM2_SMCR register). Figure 49. Triggering Timer 2 with enable of Timer 1 148/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 Figure 48, but in trigger ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Starting both timers synchronously in response to an external trigger This example, sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1. Refer to aligned, Timer 1 must be configured in master/slave mode (slave with respect to TI1, master with respect to Timer 2): ● ...
Page 150
... OCyREF PCLK TIy TIyFPy TIMxCy TIMxCLK TIMxMSK TRGI 150/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Internal/external Internal clock source: connects to STM32W108 peripheral Internal clock (PCLK) in internal clock mode. Internal Input to the clock prescaler. External trigger input (used in external timer mode 2): a clock Internal selected by TIM_EXTRIGSEL in TIMx_OR ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.2 Interrupts Each timer has its own ARM® Cortex-M3 vectored interrupt with programmable priority. Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. ...
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... Bit 0 TIM_CEN: Counter Enable 0: Counter disabled. 1: Counter enabled. Note: External clock, gated mode and encoder mode can work only if the TIM_CEN bit has been previously set by software. Trigger mode sets the TIM_CEN bit automatically through hardware. 152/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.3.2 Timer x control register 2 (TIMx_CR2) Address offset: 0xE004 (TIM1) and 0xF004 (TIM2) Reset value: Table 89. Timer x control register 2 (TIMx_CR2 Reserved Bit 7 TIM_TI1S: TI1 Selection 0: TI1M (input of the digital filter) is connected to TI1 input. 1: TI1M is connected to the TI_HALL inputs (XOR combination). ...
Page 154
... External trigger signal ETRP frequency must be at most 1 frequency. A prescaler can be enabled to reduce ETRP frequency useful with fast external clocks. 00: ETRP prescaler off. 01: Divide ETRP frequency by 2. 10: Divide ETRP frequency by 4. 11: Divide ETRP frequency by 8. 154/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Bits [11:8] TIM_ETF: External Trigger Filter This defines the frequency used to sample the ETRP signal, f digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: f Sampling 0001: f Sampling ...
Page 156
... If CC3 configured as output channel: The TIM_CC3IF flag is set. If CC3 configured as input channel: The TIM_CC3IF flag is set. The INT_TIMMISSCC3IF flag is set if the TIM_CC3IF flag was already high. The current value of the counter is captured in TMRx_CCR3 register. 156/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Bit 2 TIM_CC2G: Capture/Compare 2 Generation 0: Does nothing CC2 configured as output channel: The TIM_CC2IF flag is set. If CC2 configured as input channel: The TIM_CC2IF flag is set. The INT_TIMMISSCC2IF flag is set if the TIM_CC2IF flag was already high. The current value of the counter is captured in TMRx_CCR2 register. ...
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... An active edge on the trigger input acts like a compare match on the OC2 output. OC2 is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate OC2 output is reduced to 3 clock cycles. TIM_OC2FE acts only if the channel is configured in PWM 1 or PWM 2 mode. 158/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Doc ID 16252 Rev 13 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Bits [15:12] TIM_IC2F: Input Capture 1 Filter. (Applies only if TIM_CC2S > 0) This defines the frequency used to sample the TI2 input, Fsampling, and the length of the digital filter applied to TI2. The digital filter requires N consecutive samples in the same state before being output. ...
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... The other bits in this register have different functions in input and in output modes. The TIM_OC* fields only apply to a channel configured as an output (TIM_CCyS = 0), and the TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0). 160/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 26 25 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Bits [14:12] TIM_OC4M: Output Compare 4 Mode. (Applies only if TIM_CC4S = 0 Define the behavior of the output reference signal OC4REF from which OC4 derives. OC4REF is active high whereas OC4’s active level depends on the TIM_CC4P bit. 000: Frozen - The comparison between the output compare register TIMx_CCR4 and the counter TIMx_CNT has no effect on the outputs ...
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... See TIM_OC4FE description above. Bits [7:4] TIM_IC3F: Input Capture 1 Filter. (Applies only if TIM_CC3S > 0) See TIM_IC4F description above. Bits [3:2] TIM_IC3PSC: Input Capture 1 Prescaler. (Applies only if TIM_CC3S > 0) See TIM_IC4PSC description above. 162/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ = PCLK, no filtering. 1000 PCLK, N=2. 1001 PCLK, N=4. ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Bits [1:0] TIM_CC3S: Capture / Compare 3 Selection This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is mapped to TI3. 10: Channel is an input and is mapped to TI4. 11: Channel is an input and is mapped to TRGI. This requires an internal trigger input selected by the TIM_TS bit in the TIM_SMCR register ...
Page 164
... Address offset: 0xE024 (TIM1) and 0xF024 (TIM2) Reset value: Table 95. Timer x counter register (TIMx_CNT Bits [15:0] TIM_CNT: Counter value 164/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved TIM_CNT rw Doc ID 16252 Rev ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.3.9 Timer x prescaler register (TIMx_PSC) Address offset: 0xE028 (TIM1) and 0xF028 (TIM2) Reset value: Table 96. Timer x prescaler register (TIMx_PSC Bits [3:0] TIM_PSC: Prescaler value The prescaler divides the internal timer clock frequency. The counter clock frequency CK_CNT is equal to fCK_PSC / (2 ^ TIM_PSC) ...
Page 166
... Address offset: 0xE038 (TIM1) and 0xF038 (TIM2) Reset value: Table 99. Timer x capture/compare 2 register (TIMx_CCR2 Bits [15:0] See description in the TIMx_CCR1 register. 166/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved TIM_CCR rw 0x0000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.3.13 Timer x capture/compare 3 register (TIMx_CCR3) Address offset: 0xE03C (TIM1) and 0xF03C (TIM2) Reset value: Table 100. Timer x capture/compare 3 register (TIMx_CCR3 Bits [15:0] See description in the TIMx_CCR1 register. 10.3.14 Timer x capture/compare 4 register (TIMx_CCR4) Address offset: 0xE040 (TIM1) and 0xF040 (TIM2) Reset value: Table 101 ...
Page 168
... Enables TIM1MSK when TIM1CLK is selected as the external trigger TIM1MSK not used TIM1CLK is ANDed with the TIM1MSK input. Bits [1:0] TIM1_EXTRIGSEL Selects the external trigger used in external clock mode PCLK calibrated 1 kHz clock kHz reference clock (if available TIM1CLK pin. 168/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.3.16 Timer 2 option register (TIM2_OR) Address offset: 0xF050 Reset value: Table 103. Timer 2 option register (TIM2_OR Reserved Bit 7 TIM_REMAPC4 Selects the GPIO used for TIM2_CH4 PA2 PB4. Bit 6 TIM_REMAPC3 Selects the GPIO used for TIM2_CH3 PA1 PB3. ...
Page 170
... Bit 4 INT_TIMCC4IF: Capture or compare 4 interrupt pending. Bit 3 INT_TIMCC3IF: Capture or compare 3 interrupt pending. Bit 2 INT_TIMCC2IF: Capture or compare 2 interrupt pending. Bit 1 INT_TIMCC1IF: Capture or compare 1 interrupt pending. Bit 0 INT_TIMUIF: Update interrupt pending. 170/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved INT_TI ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 10.3.19 Timer x missed interrupt register (INT_TIMxMISS) Address offset: 0xA818 (TIM1) and 0xA81C (TIM2) Reset value: Table 106. Timer x missed interrupt register (INT_TIMxMISS INT_TI INT_TI MMIS MMIS SCC4I SCC3I Reserved Bit 12 INT_TIMMISSCC4IF: Capture or compare 4 interrupt missed. ...
Page 172
... ADC structure. Figure 51. ADC block diagram 1. For the STM32W108CC and STM32108CZ devices, the input range selection block is not present on the N Input. While the ADC Module supports both single-ended and differential inputs, the ADC input stage always operates in differential mode. Single-ended conversions are performed by connecting one of the differential inputs to VREF/2 while fully differential operation uses two external inputs ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 11.1 Functional description 11.1.1 Setup and configuration To use the ADC follow this procedure, described in more detail in the next sections: ● Configure any GPIO pins to be used by the ADC in analog mode. ● Configure the voltage reference (internal or external). ● Set the offset and gain values. ...
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... Reset initializes the offset to zero (ADC_OFFSET = 0) and gain factor to one (ADC_GAIN = 0x8000). For the STM32W108CC and STM32108CZ devices, a software mechanism is used to measure and cancel the HV buffer offset. The HV offset calculation requires two measurements with respectively CHOP = 1 and CHOP = 0 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 11.1.5 DMA The ADC DMA channel writes converted data, which incorporates the offset/gain correction, into a DMA buffer in RAM. The ADC DMA buffer is defined by two registers: ● ADC_DMABEG is the start address of the buffer and must be even. ● ADC_DMASIZE specifies the size of the buffer in 16-bit samples, or half its length in bytes ...
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... The input buffers are enabled for the ADC P and N inputs by setting the ADC_HVSELP and ADC_HVSELN bits respectively, in the ADC_CFG register. The ADC accuracy is reduced when the input buffer is selected. 176/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Analog source at ADC GPIO pin VREF/2 Internal connection Calibration ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Sample time ADC sample time is programmed by selecting the sampling clock and the clocks per sample. ● The sampling clock may be either 1 MHz or 6 MHz. If the ADC_1MHZCLK bit in the ADC_CFG register is clear, the 6 MHz clock is used set, the 1 MHz clock is selected ...
Page 178
... Table 111 shows the equations used to calculate the gain and offset correction values. Table 111. ADC gain and offset correction equations Gain Offset (after applying gain correction) 178/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Calibration Doc ID 16252 Rev 13 Correction value 16384 × ------------------------------------------ ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Equation notes ● All N are 16-bit two’s complement numbers. ● sampling of ground. Due to the ADC's internal design, VGND does not yield GND the minimum two’s complement value 0x8000 as the conversion result. Instead, VGND yields a two’s complement value close to 0xE000 when the input buffer is not selected. ...
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... ADC_HVSELN: Select voltage range for the N input channel. 0: Low voltage range (input buffer disabled). 1: High voltage range (input buffer enabled). Note: For the STM32W108CC and STM32W108CZ, the HVSELN register allows the chopper to be controlled. Bits [10:7] ADC_MUXP: Input selection for the P channel. ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 11.3.2 ADC offset register (ADC_OFFSET) Address offset: 0xD008 Reset value: Table 113. ADC offset register (ADC_OFFSET Bits [15:0] ADC_OFFSET_FIELD: 16-bit signed offset added to the basic ADC conversion result before gain correction is applied. 11.3.3 ADC gain register (ADC_GAIN) ...
Page 182
... Bit 1 ADC_DMAOVF: DMA overflow: occurs when an ADC result is ready and the DMA is not active. Cleared by DMA reset. Bit 0 ADC_DMAACT: DMA status: reads 1 if DMA is active. 182/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved Reserved ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 11.3.6 ADC DMA begin address register (ADC_DMABEG) Address offset: 0xD018 Reset value: Table 117. ADC DMA begin address register (ADC_DMABEG Reserved Bits [13:0] ADC_DMABEG: ADC buffer start address. Caution: This must be an even address - the least significant bit of this register is fixed at zero by hardware ...
Page 184
... Table 120. ADC DMA count register (ADC_DMACNT Reser ved Bits [12:0] ADC_DMACNT_FIELD: DMA count: the number of 16-bit conversion results that have been written to the buffer. 184/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x2000 0000 Reserved ADC_DMACUR_FIELD r 0x0000 0000 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 11.3.10 ADC interrupt flag register (INT_ADCFLAG) Address offset: 0xA810 Reset value: Table 121. ADC interrupt flag register (INT_ADCFLAG Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 11.3.11 ADC interrupt configuration register (INT_ADCCFG) Address offset: 0xA850 Reset value: Table 122 ...
Page 186
... ARM® Cortex-M3 NVIC, while exceptions 16 (Timer 1) through 32 (Debug) are the peripheral interrupts specific to the STM32W108 peripherals. The peripheral interrupts are listed in greater detail in 186/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Section 12.2: Event manager Table 123 lists the entire exception table. Exceptions 0 ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Table 123. NVIC exception table Exception - Reset NMI Hard Fault Memory Fault Bus Fault Usage Fault - SVCall Debug Monitor - PendSV SysTick Timer 1 Timer 2 Management Baseband Sleep Timer Serial Controller 1 Serial Controller 2 Security MAC Timer MAC Transmit MAC Receive ...
Page 188
... The second-level interrupt registers, which provide control of the second-level Event Manager peripheral interrupts, are described in For further information on the NVIC and Cortex-M3 exceptions, refer to the ARM® Cortex- M3 Technical Reference Manual and the ARM ARMv7-M Architecture Reference Manual. 188/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ Position 31 IRQD peripheral interrupt. 32 Debug peripheral interrupt ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 12.1.1 Non-maskable interrupt (NMI) The non-maskable interrupt (NMI special case. Despite being one of the 10 standard ARM® Cortex-M3 NVIC interrupts sourced from the Event Manager like a peripheral interrupt. The NMI has two second-level sources; failure of the 24 MHz crystal and watchdog low water mark ...
Page 190
... The INT_periphFLAG register bits are designed to remain set if the second-level interrupt event re-occurs at the same moment as the INT_periphFLAG register bit is being cleared. This ensures the re-occurring second-level interrupt event is not missed. 190/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ OR INT_periphCFG AND read ...
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... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ If another enabled second-level interrupt event of the same type occurs before the first interrupt event is cleared, the second interrupt event is lost because no counting or queuing is used. However, this condition is detected and stored in the top-level INT_MISS register to facilitate software detection of such problems. The INT_MISS register is "acknowledged" in the same way as the INT_periphFLAG register-by writing a 1 into the corresponding bit to be cleared ...
Page 192
... Table 124. NVIC and EM peripheral interrupt map NVIC Interrupt (top level) 16 INT_DEBUG 15 INT_IRQD 14 INT_IRQC 13 INT_IRQB 12 INT_IRQA 11 INT_ADC 10 INT_MACRX 9 INT_MACTX 8 INT_MACTMR 7 INT_SEC 6 INT_SC2 192/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ EM Interrupt (second level) 5 INT_ADCFLAG register 4 INT_ADCOVF 3 INT_ADCSAT 2 INT_ADCULDFULL 1 INT_ADCULDHALF 0 INT_ADCDATA INT_SC2FLAG register 12 INT_SCTXULDB 4 11 INT_SCTXULDA 3 10 INT_SCRXULDB 2 9 ...
Page 193
... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 12.3 Nested vectored interrupt controller (NVIC) interrupts 12.3.1 Top-level set interrupts configuration register (INT_CFGSET) Address: Reset value: Table 125. Top-level set interrupts configuration register (INT_CFGSET INT_IR INT_IR INT_IR INT_IR INT_A ...
Page 194
... Bit 3 INT_BB: Write 1 to disable baseband interrupt. (Writing 0 has no effect.) Bit 2 INT_MGMT: Write 1 to disable management interrupt. (Writing 0 has no effect.) Bit 1 INT_TIM2: Write 1 to disable timer 2 interrupt. (Writing 0 has no effect.) Bit 0 INT_TIM1: Write 1 to disable timer 1 interrupt. (Writing 0 has no effect.) 194/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 ...
Page 195
... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 12.3.3 Top-level set interrupts pending register (INT_PENDSET) Address: 0xE000E200 Reset value: Table 127. Top-level set interrupts pending register (INT_PENDSET INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA Bit 16 INT_DEBUG: Write 1 to pend debug interrupt. (Writing 0 has no effect.) Bit 15 INT_IRQD: Write 1 to pend IRQD interrupt ...
Page 196
... Bit 3 INT_BB: Write 1 to unpend baseband interrupt. (Writing 0 has no effect.) Bit 2 INT_MGMT: Write 1 to unpend management interrupt. (Writing 0 has no effect.) Bit 1 INT_TIM2: Write 1 to unpend timer 2 interrupt. (Writing 0 has no effect.) Bit 0 INT_TIM1: Write 1 to unpend timer 1 interrupt. (Writing 0 has no effect.) 196/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 ...
Page 197
... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 12.3.5 Top-level active interrupts register (INT_ACTIVE) Address: 0xE000E300 Reset value: Table 129. Top-level active interrupts register (INT_ACTIVE INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA Bit 16 INT_DEBUG: Debug interrupt active. ...
Page 198
... Bit 7 INT_MISSSEC: Security interrupt missed. Bit 6 INT_MISSSC2: Serial controller 2 interrupt missed. Bit 5 INT_MISSSC1: Serial controller 1 interrupt missed. Bit 4 INT_MISSSLEEP: Sleep timer interrupt missed. Bit 3 INT_MISSBB: Baseband interrupt missed. Bit 2 INT_MISSMGMT: Management interrupt missed. 198/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 0x0000 0000 Reserved ...
Page 199
... STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 12.3.7 Auxiliary fault status register (SCS_AFSR) Address: Reset value: Table 131. Auxiliary fault status register (SCS_AFSR Bit 3 WRONGSIZE A bus fault resulted from an 8-bit or 16-bit read or write of an APB peripheral register. This fault can also result from an unaligned 32-bit access. ...
Page 200
... JTDI ● SWDIO/JTMS ● SWCLK/JTCK Since these pins can be repurposed, refer to page 15 and Section 8: General-purpose input/outputs on page 58 descriptions and configurations. 200/232 STM32W108HB STM32W108CC STM32W108CB STM32W108CZ SWJ-DAP SWJ-DP SW interface Control and AP interface JTAG interface Section 3: Pinout and pin description on Doc ID 16252 Rev 13 ...