STM32W108C8 STMicroelectronics, STM32W108C8 Datasheet
STM32W108C8
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STM32W108C8 Summary of contents
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... Support for external power amplifier – Small 7x7 mm 48-pin VFQFPN package Applications ■ RF4CE products and remote controls ■ 6LoWPAN and custom protocols ■ 802.15.4 based network protocols (standard and proprietary) Doc ID 018587 Rev 2 STM32W108C8 VFQFPN48 ( mm) 1/215 www.st.com 1 ...
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... Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARM® Cortex™-M3 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Direct memory access (DMA) to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RAM memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Rx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 RSSI and CCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Tx baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TX_ACTIVE and nTX_ACTIVE signals . . . . . . . . . . . . . . . . . . . . . . . . . 30 Internally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Externally regulated power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 6.2.2 6.2.3 6.2.4 6.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.4 System timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5.1 6.5.2 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Option byte error .34 Debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 JTAG reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Deep sleep reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Reset recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset event source register (RESET_EVENT .36 High-frequency internal RC oscillator (OSCHF High-frequency crystal oscillator (OSC24M Low-frequency internal RC oscillator (OSCRC Low-frequency crystal oscillator (OSC32K) ...
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... Port x output set register (GPIO_PxSET Port x wakeup monitor register (GPIO_PxWAKE GPIO wakeup filtering register (GPIO_WAKEFILT Interrupt x select register (GPIO_IRQxSEL GPIO interrupt x configuration register (GPIO_INTCFGx GPIO interrupt flag register (INT_GPIOFLAG GPIO debug configuration register (GPIO_DBGCFG GPIO debug status register (GPIO_DBGSTAT Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 9 Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.3.1 9.3.2 9.3.3 9.4 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.4.1 9.4.2 9.4.3 9.4.4 9.5 Inter-integrated circuit interfaces (I2C 9.5.1 9.5.2 9.5.3 9.6 Universal asynchronous receiver / transmitter (UART 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.8 Serial controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.8.1 9.8.2 9.8.3 9.8.4 9.9 SPI master mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.10 SPI slave mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.11 Inter-integrated circuit (I2C) interface registers . . . . . . . . . . . . . . . . . . . . 95 Setup and configuration ...
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... Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Down-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Center-aligned mode (up/down counting .115 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Internal clock source (CK_INT .118 External clock source mode .118 External clock source mode .120 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 10.1.9 10.1.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.1.11 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.1.12 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.1.13 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 133 10.1.14 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.1.15 Timer signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.3 General-purpose timer (1 and 2) registers . . . . . . . . . . . . . . . . . . . . . . . 142 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.3.10 Timer x auto-reload register (TIMx_ARR 155 10.3.11 Timer x capture/compare 1 register (TIMx_CCR1 155 10 ...
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... ADC DMA configuration register (ADC_DMACFG 170 ADC DMA status register (ADC_DMASTAT 170 ADC DMA begin address register (ADC_DMABEG 171 ADC DMA buffer size register (ADC_DMASIZE 171 ADC DMA current address register (ADC_DMACUR 171 ADC DMA count register (ADC_DMACNT 172 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 12.1.1 12.1.2 12.2 Event manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 12.3 Nested vectored interrupt controller (NVIC) interrupts . . . . . . . . . . . . . . 181 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 13 Debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 13.1 STM32W108 JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 14.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.3.1 14.3.2 14.3.3 14.4 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14.5 Clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.5.1 14.5.2 14.5.3 14.5.4 Non-maskable interrupt (NMI 176 Faults ...
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... DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.7 Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14.8 Non-RF system electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 206 14.9 RF electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 14.9.1 14.9.2 14.9.3 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 9/215 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Doc ID 018587 Rev 2 STM32W108C8 ...
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... The STM32W108C8 has 64 Kbytes of embedded Flash memory and 8 Kbytes of integrated RAM for data and program storage. The STM32W108C8 HAL software employs an effective wear-leveling algorithm that optimizes the lifetime of the embedded Flash ...
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... Description The STM32W108C8 offers a number of advanced power management features that enable long battery life. A high-frequency internal RC oscillator allows the processor core to begin code execution quickly upon waking. Various deep sleep modes are available with less than 1 µA power consumption while retaining RAM contents. To support user-defined applications, on-chip peripherals include UART, SPI well GPIOs ...
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... MHz internal RC oscillator, an optional low frequency 32.768 kHz external crystal oscillator, and a 10 kHz internal RC oscillator. The STM32W108C8 has an ultra low power, deep sleep state with a choice of clocking modes. The sleep timer can be clocked with either the external 32.768 kHz crystal oscillator or with a 1 kHz clock derived from the internal 10 kHz RC oscillator ...
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... Description can be disabled for the lowest power mode. In the lowest power mode, only external events on GPIO pins will wake up the chip. The STM32W108C8 has a fast startup time (typically 100 µs) from deep sleep to the execution of the first ARM® Cortex-M3 instruction. ...
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... STM32W108C8 2 Documentation conventions Table 1. Description of abbreviations used for bitfield access Abbreviation Read/Write (rw) Read-only (r) Write only (w) Read/Write in (MPU) Privileged mode only (rws) 1. The conditions under which the hardware (core) sets or clears this field are explained in details in the bitfield description, as well as the events that may be generated by writing to the bit. ...
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... Power 1.8V RF supply (LNA and PA) O Differential (with RF_TX_ALT_N) transmitter output (optional) O Differential (with RF_TX_ALT_P) transmitter output (optional) Power 1.8V IF supply (mixers and filters) Doc ID 018587 Rev 2 STM32W108C8 PB0, VREF, IRQA, TRACECLK, TIM1CLK, TIM2MSK 36 PC4, JTMS, SWDIO 35 PC3, JTDI 34 PC2, JTDO, SWO 33 SWCLK, JTCK ...
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... TIM1_CH4 REG_EN Direction I Bias setting resistor Power Analog pad supply (1.8V) I/O Digital I/O Logic-level control for external Rx/Tx switch. The STM32W108C8 baseband controls TX_ACTIVE and drives it high (VDD_PADS) O when in Tx mode. Select alternate output function with GPIO_PCCFGH[7:4] I Active low chip reset (internal pull-up) I/O Digital I/O 32 ...
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... Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[7] O Enable with SC1_UARTCFG[5] Select UART with SC1_MODE Select alternate output function with GPIO_PBCFGH[3:0] SPI slave select of Serial Controller 1 I Enable slave with SC1_SPICFG[4] Select SPI with SC1_MODE Doc ID 018587 Rev 2 STM32W108C8 Description ...
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... STM32W108C8 Table 2. Pin descriptions (continued) Pin no. Signal PA0 TIM2_CH1 (see also Pin 30) 21 SC2MOSI PA1 TIM2_CH3 (see also Pin 19) SC2SDA 22 SC2MISO 23 VDD_PADS Direction I/O Digital I/O Timer 2 channel 1 output Disable remap with TIM2_OR[4] O Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[3:0] I Timer 2 channel 1 input ...
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... TIM2_OR[5] O Enable trace interface in ARM core Select alternate output function with GPIO_PACFGL[15:12] Timer 2 channel 2 output Disable remap with TIM2_OR[5] O Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[15:12] I Timer 2 channel 2 input. Disable remap with TIM2_OR[5]. Doc ID 018587 Rev 2 STM32W108C8 Description ...
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... STM32W108C8 Table 2. Pin descriptions (continued) Pin no. Signal PA4 ADC4 PTI_EN 26 TRACEDATA2 PA5 ADC5 PTI_DATA 27 nBOOTMODE TRACEDATA3 28 VDD_PADS PA6 High current 29 TIM1_CH3 Direction I/O Digital I/O Analog ADC Input 4. Select analog function with GPIO_PACFGH[3:0]. Frame signal of Packet Trace Interface (PTI). O Disable trace interface in ARM core. ...
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... Either disable timer output in TIM2_CCER or disable remap with TIM2_OR[4] O Select UART with SC1_MODE Select alternate output function with GPIO_PBCFGL[7:4] Timer 2 channel 1 output Enable remap with TIM2_OR[4] O Enable timer output in TIM2_CCER Select alternate output function with GPIO_PACFGL[7:4] I Timer 2 channel 1 input. Disable remap with TIM2_OR[4]. Doc ID 018587 Rev 2 STM32W108C8 Description ...
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... STM32W108C8 Table 2. Pin descriptions (continued) Pin no. Signal PB2 SC1MISO SC1MOSI 31 SC1SCL SC1RXD TIM2_CH2 (see also Pin 25) SWCLK 32 JTCK PC2 JTDO 33 SWO PC3 34 JTDI Direction I/O Digital I/O SPI master data in of Serial Controller 1 I Select SPI with SC1_MODE Select master with SC1_SPICR SPI slave data in of Serial Controller 1 ...
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... Enable trace interface in ARM core Select alternate output function with GPIO_PCCFGL[7:4] Synchronous CPU trace data bit 0 Select 1 4-wire synchronous trace interface in ARM core O Enable trace interface in ARM core Select alternate output function with GPIO_PCCFGL[7:4] Power 1.8 V supply (flash, RAM) Doc ID 018587 Rev 2 STM32W108C8 Description ...
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... STM32W108C8 Table 2. Pin descriptions (continued) Pin no. Signal PC0 High current JRST 40 (1) IRQD TRACEDATA1 PB7 High current ADC2 (1) 41 IRQC TIM1_CH2 PB6 High current ADC1 42 IRQB TIM1_CH1 PB5 ADC0 43 TIM2CLK TIM1MSK 44 VDD_CORE 45 VDD_PRE 46 VDD_SYNTH 47 OSCB Direction Digital I/O I/O Either enable with GPIO_DBGCFG[5], ...
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... GND 1. IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the using the GPIO_IRQCSEL and GPIO_IRQDSEL registers. 25/215 Direction I/O 24 MHz crystal oscillator or external clock input Ground Ground supply pad in the bottom center of the package. Doc ID 018587 Rev 2 STM32W108C8 Description ...
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... STM32W108C8 4 Embedded memory Figure 3. STM32W108C8 memory mapping Doc ID 018587 Rev 2 Embedded memory 26/215 ...
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... FIB. 4.2 Random-access memory The STM32W108C8 has 8 Kbytes of static RAM on-chip. The start of RAM is mapped to address 0x20000000. Although the ARM® Cortex-M3 allows bit band accesses to this address region, the standard MPU configuration does not permit use of the bit-band feature. ...
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... Memory protection unit The STM32W108C8 includes the ARM® Cortex-M3 Memory Protection Unit, or MPU. The MPU controls access rights and characteristics eight address regions, each of which may be divided into eight equal sub-regions. Refer to the ARM® Cortex-M3 Technical Reference Manual (DDI 0337A) for a detailed description of the MPU ...
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... RSSI and CCA The STM32W108C8 calculates the RSSI over every 8-symbol period as well as at the end of a received packet. The linear range of RSSI is specified least 40 dB over temperature. At room temperature, the linear range is approximately 60 dB (-90 dBm to -30 dBm input signal) ...
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... This allows the ARM® Cortex-M3 CPU to provide greater bandwidth to application and network operations. In addition, the hardware acts as a first-line filter for unwanted packets. The STM32W108C8 MAC uses a DMA interface to RAM to further reduce the overall ARM® Cortex-M3 CPU interaction when transmitting or receiving packets. ...
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... IEEE 802.15.4 timing and slotted/unslotted timing 5.5 Packet trace interface (PTI) The STM32W108C8 integrates a true PHY-level PTI for effective network-level debugging. It monitors all the PHY Tx and Rx packets between the MAC and baseband modules without affecting their normal operation. It cannot be used to inject packets into the PHY/MAC interface ...
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... STM32W108C8 6 System modules System modules encompass power, resets, clocks, system timers, power management, and encryption. Figure 4 Figure 4. System module block diagram recomended connections for internal regulator External Regulator optional connections for external regulator shows these modules and how they interact. Wakeup Recording ...
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... The STM32W108C8 contains three power domains: ● An "always on domain" containing all logic and analog cells required to manage the STM32W108C8's power modes, including the GPIO controller and sleep timer. This domain must remain powered. ● A "core domain" containing the CPU, Nested Vectored Interrupt Controller (NVIC), and peripherals ...
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... JTAG standard. This input acts independently of all other reset sources and, when asserted, does not reset any on-chip hardware except for the JTAG TAP. If the STM32W108C8 is in the Serial Wire mode or if the SWJ is disabled, this input has no effect. 192. ...
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... The Power Management module allows a special emulated deep sleep state that retains memory and core domain power while in deep sleep. 6.2.2 Reset recording The STM32W108C8 records the last reset condition that generated a restart to the system. The reset conditions recorded are: ● POWER_HV ● ...
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... STM32W108C8 ● PRESETHV ● PRESETLV Table 3 shows which reset sources generate certain resets. Table 3. Generated resets Reset source POR HV POR LV (in deep sleep) POR LV (not in deep sleep) RSTB Watchdog reset Software reset Option byte error Normal deep sleep Emulated deep sleep Debug reset 6 ...
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... Bit 1 POWER_LV: When set to ‘1’, the reset is due to the application of a Core power supply (or previously failed). Bit 0 POWER_HV: Always set to ‘1’, Normal power applied 6.3 Clocks The STM32W108C8 integrates four oscillators: ● High frequency RC oscillator ● 24 MHz crystal oscillator ● ...
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... STM32W108C8 Figure 5 shows a block diagram of the clocks in the STM32W108C8. This simplified view shows all the clock sources and the general areas of the chip to which they are routed. Figure 5. Clocks block diagram 12MHz RC 24MHz XTAL 10kHz RC 32kHz XTAL 32kHz digital in Watchdog counter ...
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... Section 14.5.4: Low frequency external clock characteristics on page 6.3.5 Clock switching The STM32W108C8 has two switching mechanisms for the main system clock, providing four clock modes. The register bit OSC24M_SEL in the OSC24M_CTRL register switches between the high- frequency RC oscillator (OSCHF) and the high-frequency crystal oscillator (OSC24M) as the main system clock (SCLK) ...
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... STM32W108C8 In addition to these modes, further automatic control is invoked by hardware when flash programming is enabled. To ensure accuracy of the flash controller's timers, the FCLK frequency is forced to 12 MHz during flash programming and erase operations. Table 5. System clock modes OSC24M_SEL CPU_CLK_SEL 0 (OSCHF) 0 (Normal CPU) 0 (OSCHF) ...
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... WDOG_DIS register bit. 6.4.2 Sleep timer The STM32W108C8 integrates a 32-bit timer dedicated to system timing and waking from sleep at specific times. The sleep timer can use either the calibrated 1 kHz reference(CLK1K), or the 32 kHz crystal clock (CLK32K). The default clock source is the internal 1 kHz clock ...
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... STM32W108C8 6.4.3 Event timer The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see switching on page 6 ...
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... Reserved SLEEP TMR_ Reserved SLEEPTMR_CLKDIV DBGPA USE where 15. 0x0000 0000 Doc ID 018587 Rev 2 STM32W108C8 Reserved SLEEP TMR_ CLKSE L rw ...
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... STM32W108C8 Sleep timer count high register (SLEEPTMR_CNTH) Table 11 Bits [15:0] SLEEPTMR_CNTH_FIELD: Sleep timer counter high value [31:16]. Reading this register updates the SLEEP_COUNT_L for subsequent reads. Sleep timer count low register (SLEEPTMR_CNTL) Address: Reset value: Table 12. Sleep timer count low register (SLEEPTMR_CNTL) ...
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... FFFF Reserved SLEEPTMR_CMPAL rw 0x4000 6020 0x0000 FFFF Reserved SLEEPTMR_CMPBH rw Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Bits [15:0] SLEEPTMR_CMPBH_FIELD: Sleep timer compare B high value [31:16]. Sleep timer compare value, writing updates COMP_B_H (directly) and COMP_B_L (from hold register). Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’. If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated. ...
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... Reserved Reserved r 0x4000 0008 0x0000 0002 Reserved Reserved r Doc ID 018587 Rev 2 STM32W108C8 INT_ SLEEP TMR CMPB SLEEP TMR_ CLK10K ...
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... Wake sources When in deep sleep the STM32W108C8 can be returned to the running state in a number of ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2. The following wake sources are available in both deep sleep 1 and 2. ● ...
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... The Wakeup Recording module monitors all possible wakeup sources. More than one wakeup source may be recorded because events are continually being recorded (not just in deep-sleep), since another event may happen between the first wake event and when the STM32W108C8 wakes up. 49/215 Doc ID 018587 Rev 2 ...
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... STM32W108C8 6.5.2 Basic sleep modes The power management state diagram in management controller. Figure 6. Power management state diagram DEEP SLEEP PRE- DEEP SLEEP CSYSPWRUPREQ & INHIBIT Figure 6 shows the basic operation of the power CDBGPWRUPREQ set CDBGPWRUPREQ cleared Deep sleep requested (WFI instruction with SLEEP_DEEP=1) ...
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... CSYSPWRUPREQ). This pre-deep sleep state ensures debug operations are not interrupted. In the deep sleep state the STM32W108C8 waits for a wake up event which will return it to the running state. In powering up the core logic the ARM® Cortex-M3 is put through a reset cycle and ST software restores the stack and application state to the point where deep sleep was invoked ...
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... STM32W108C8 debugger initiates access while the STM32W108C8 is in deep sleep, the SWJ intelligently holds off the debugger for a brief period of time until the STM32W108C8 is properly powered and ready. For more information regarding the SWJ and the interaction of debuggers with deep sleep, contact ST support for Application Notes and ARM® ...
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... Integrated voltage regulator 7 Integrated voltage regulator The STM32W108C8 integrates two low dropout regulators to provide 1.8 V and 1.25 V power supplies. The 1V8 regulator supplies the analog and memories, and the 1V25 regulator supplies the digital core. In deep sleep the voltage regulators are disabled. When enabled, the 1V8 regulator steps down the pads supply voltage (VDD_PADS) from a nominal 3 ...
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... Parameter 1V8 regulator start-up time 1V25 regulator start-up time An external 1.8 V regulator may replace both internal regulators. The STM32W108C8 can control external regulators during deep sleep using open-drain GPIO PA7, as described in Section 8: General-purpose sleep to disable the external regulator and an external pull-up is required to release this signal to indicate that supply voltage should be provided ...
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... General-purpose input/outputs 8 General-purpose input/outputs The STM32W108C8 has 24 multi-purpose GPIO pins that may be individually configured as: ● General purpose output ● General purpose open-drain output ● Alternate output controlled by a peripheral device ● Alternate open-drain output controlled by a peripheral device ● Analog ● ...
Page 57
... GPIO_PxSET (set output data register) sets bits in GPIO_PxOUT. ● GPIO_PxWAKE (wake monitor register) specifies the pins that can wake the STM32W108C8. In addition to these registers, each port has a pair of configuration registers, GPIO_PxCFGH and GPIO_PxCFGL. These registers specify the basic operating mode for the port's pins ...
Page 58
... Push-pull output mode only for SPI master mode 0xB SCLK pins. Table 22 indicates the GPIO mapping for Timer 2 outputs GPIO mapping selected by TIM2_OR bit Option register bit TIM2_OR[4] TIM2_OR[5] TIM2_OR[6] TIM2_OR[7] Doc ID 018587 Rev 2 STM32W108C8 Description Section 10: General-purpose timers 0 1 PA0 PB1 PA3 PB2 PA1 PB3 PA2 ...
Page 59
... While in reset and during the subsequent power-on-reset startup delay (512 high-frequency RC oscillator periods), PA5 is automatically configured as an input with a pull-up resistor. At the end of this time, the STM32W108C8 samples nBOOTMODE: a high level selects normal startup, and a low level selects the boot loader. After nBOOTMODE has been sampled, PA5 is configured as a floating input ...
Page 60
... GPIO_PxOUT register controls the output. The GPIO_PxSET and GPIO_PxCLR registers can atomically set and clear bits within GPIO_PxOUT register. These set and clear registers simplify software using the output port because they eliminate the need to disable interrupts to perform an atomic read-modify-write operation of GPIO_PxOUT. 59/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... The GPIO_PxWAKE registers specify which GPIOs are monitored to wake the processor GPIO's wake enable bit is set in GPIO_PxWAKE, then a change in the logic value of that GPIO causes the STM32W108C8 to wake from deep sleep. The logic values of all GPIOs are captured by hardware upon entering sleep. If any GPIO's logic value changes while in sleep and that GPIO's GPIO_PxWAKE bit is set, then the STM32W108C8 will wake from deep sleep ...
Page 62
... In order to use GPIO pins to wake the STM32W108C8 from deep sleep, the GPIO_WAKE bit in the WAKE_SEL register must be set. Waking up from GPIO activity does not work with pins configured for analog mode since the digital logic input is always set to 1 when in analog mode ...
Page 63
... SPI slave mode interface. Refer to Section 12: Interrupts on page 174 STM32W108C8 interrupt system. 8.3 Debug control and status Two GPIO registers are largely concerned with debugger functions. GPIO_DBGCFG can disable debugger operation, but has other miscellaneous control bits as well. ...
Page 64
... TIM2_CH4 , UART_RTS ADC0 ADC1 TIM1_CH1 ADC2 TIM1_CH2 TRACEDATA1 ADC3 TRACEDATA0, SWO (6) JTDO , SWO (7) SWDIO TX_ACTIVE OSC32B nTX_ACTIVE OSC32A Doc ID 018587 Rev 2 STM32W108C8 Output current Input drive TIM1CLK, TIM2MSK, Standard IRQA (4) TIM2_CH1 , SC1SDA Standard (4) TIM2_CH2 , SC1MISO, SC1MOSI, Standard SC1SCL, SC1RXD (4) TIM2_CH3 , Standard ...
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... STM32W108C8 8.5 General-purpose input / output (GPIO) registers 8.5.1 Port x configuration register (Low) ( Address offset: 0xB000 (GPIO_PACFGL), 0xB400 (GPIO_PBCFGL) and 0xB800 (GPIO_PCCFGL) Reset value: Table 26. Port x configuration register (Low Px3_CFG rw Bits [15:12] Px3_CFG: GPIO configuration control. 0x0: Analog, input or output (GPIO_PxIN always reads 1). ...
Page 66
... Bit 2 Px2: Input level at pin Px2. Bit 1 Px1: Input level at pin Px1. Bit 0 Px0: Input level at pin Px0. 65/215 0x0000 0000 Reserved Px7 rw Doc ID 018587 Rev 2 STM32W108C8 Px6 Px5 Px4 Px3 Px2 rw ...
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... STM32W108C8 8.5.4 Port x output data register (GPIO_PxOUT) Address offset: 0xB00C (GPIO_PAOUT), 0xB40C (GPIO_PBOUT) Reset value: Table 29. Port x output data register (GPIO_PxOUT Reserved Bit 7 Px7: Output data for Px7. Bit 6 Px6: Output data for Px6. Bit 5 Px5: Output data for Px5. ...
Page 68
... Reserved Px7 rw and 0xBC10 (GPIO_PCWAKE) 0x0000 0000 Reserved Px7 rw Doc ID 018587 Rev 2 STM32W108C8 Px6 Px5 Px4 Px3 Px2 ...
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... STM32W108C8 Bit 7 Px7: Write 1 to enable wakeup monitoring of Px7. Bit 6 Px6: Write 1 to enable wakeup monitoring of Px6. Bit 5 Px5: Write 1 to enable wakeup monitoring of Px5. Bit 4 Px4: Write 1 to enable wakeup monitoring of Px4. Bit 3 Px3: Write 1 to enable wakeup monitoring of Px3. ...
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... Reserved GPIO_I GPIO_INTMOD NTFILT rw Doc ID 018587 Rev 2 STM32W108C8 0x0D: PB5. 0x0E: PB6. 0x0F: PB7. 0x10: PC0. 0x11: PC1. 0x12: PC2. 0x13: PC3. 0x14: PC4. 0x15: PC5. 0x16: PC6. 0x17: PC7. 0x18 - 0x1F: Reserved ...
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... STM32W108C8 8.5.11 GPIO interrupt flag register (INT_GPIOFLAG) Address offset: 0xA814 Reset value: Table 36. GPIO interrupt flag register (INT_GPIOFLAG Bit 3 INT_IRQDFLAG: IRQD interrupt pending. Bit 2 INT_IRQCFLAG: IRQC interrupt pending. Bit 1 INT_IRQBFLAG: IRQB interrupt pending. Bit 0 INT_IRQAFLAG: IRQA interrupt pending. ...
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... Debugger interface not forced active. 1: Debugger interface forced active by debugger cable. Bit 0 GPIO_SWEN: Status of Serial Wire interface. 0: Not enabled by SWJ-DP. 1: Enabled by SWJ-DP. 71/215 0x0000 0000 Reserved Reserved Doc ID 018587 Rev 2 STM32W108C8 GPIO_ BOOT Reserv MODE ...
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... STM32W108C8 9 Serial interfaces 9.1 Functional description The STM32W108C8 has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous and asynchronous serial communications. ● SPI (Serial Peripheral Interface), master or slave 2 ● (Inter-Integrated Circuit), master only ● UART (Universal Asynchronous Receiver/Transmitter), SC1 only ● ...
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... SCx_I2CCTRL1 SCx_DATA SCx_I2CCTRL2 TX-FIFO SCx_DMACTRL SCx_RXCNTA/B SCx_RXCNTSAVED DMA SCx_TX/RXBEGA/B Controller SCx_TX/RXENDA/B SCx_DMASTAT SCx_RXERRA/B RX-FIFO 100. Doc ID 018587 Rev 2 STM32W108C8 Baud Generator UART Controller SPI Slave Controller SPI Master Controller Clock Generator Master Controller SCx_TXCNT Table 39 shows how to configure GPIO Section 9.13: ...
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... STM32W108C8 Table 39. SC1 GPIO usage and configuration Interface SC1MOSI alternate SPI - Master output (push-pull) SC1MISO alternate SPI - Slave output (push-pull) SC1SDA alternate Master output (open-drain) TXD alternate UART output (push-pull) 1. used if RTS/CTS hardware flow control is enabled. Table 40. SC2 GPIO usage and configuration ...
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... LIN 75). The bits SC_SPIPOL, SC_SPIPHA, and SC_SPIORD Frame formats SCLK out MOSI TX[7] TX[6] TX[5] out MISO RX[7] RX[6] RX[5] in SCLK out MOSI TX[7] TX[6] TX[5] out MISO RX[7] RX[6] RX[5] in Doc ID 018587 Rev 2 STM32W108C8 MISO SCLK Input Output Alternate Output (push-pull) Input Special SCLK mode PB2 PB3 PA1 PA2 )x2 EXP 1 + TX[4] TX[3] TX[2] TX[1] TX[0] RX[4] RX[3] RX[2] RX[1] RX[0] TX[4] TX[3] TX[2] TX[1] ...
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... STM32W108C8 Table 42. SPI master mode formats (continued) SCx_SPICFG (1) SC_SPIxxx MST ORD PHA POL Same as above except data is sent LSB first instead of MSB first. 1. The notation xxx means that the corresponding column header below is inserted to form the field name. ...
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... MISO (Master In, Slave Out) - outputs serial data to the master ● SCLK (Serial Clock) - clocks data transfers on MOSI and MISO ● nSSEL (Slave Select) - enables serial communication with the slave The GPIO pins that can be assigned to these signals are shown in 77/215 Doc ID 018587 Rev 2 STM32W108C8 Table 43. ...
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... STM32W108C8 Table 43. SPI slave GPIO usage Parameter Direction GPIO configuration SC1 pin SC2 pin 9.4.1 Setup and configuration Both serial controllers, SC1 and SC2, support SPI slave mode. SPI slave mode is enabled by the following register settings: ● The serial controller mode register, SCx_MODE, is ‘2’. ...
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... SC_SPITXFREE bit in the SCx_SPISTAT register is cleared. Shifting out a transmit character to the MISO pin causes the SC_SPITXFREE bit in the SCx_SPISTAT register to get set. When the transmit FIFO empties and the last character has been shifted out, the SC_SPITXIDLE bit in the SCx_SPISTAT register is set. 79/215 Frame format RX[7] RX[6] RX[5] RX[4] RX[3] TX[7] TX[6] TX[5] TX[4] TX[3] Doc ID 018587 Rev 2 STM32W108C8 RX[2] RX[1] RX[0] TX[2] TX[1] TX[0] ...
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... To enable CPU interrupts, set desired interrupt bits in the second level INT_SCxCFG register, and also enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register. 9.5 Inter-integrated circuit interfaces (I Both STM32W108C8 serial controllers SC1 and SC2 include an Inter-integrated circuit 2 interface (I C) master controller with the following features: ● ...
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... C (100 kbps) and Fast-Mode I SCx_RATELIN Bus specification requires the minimum low period of SCL to be Figure 47 summarizes these frames. Doc ID 018587 Rev 2 STM32W108C8 2 C master controllers. Because the SCL Input / Output Alternate Output (open drain) PB2 PA2 2 C controller ...
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... STM32W108C8 2 Table 47 master frame segments SCx_TWICTRL1 (1) SC_TWIxxxx START SEND RECV STOP The notation xxx means that the corresponding column header below is inserted to form the field name. ...
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... SCx_TWISTAT register can be used for waiting. Now the SC_TWIRXNAK bit in the SCx_TWISTAT register indicates if a NACK or ACK was received from an I 83/215 IDLE START Segment STOP Segment RECEIVE Segment with NACK Doc ID 018587 Rev 2 STM32W108C8 TRANSMIT Segment NO received ACK ? YES RECEIVE Segment with ACK 2 C slave device. ...
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... If RTS/CTS flow control is enabled, these two signals are also used: ● nRTS (Request To Send) - indicates the STM32W108C8 is able to receive data RXD ● nCTS (Clear To Send) - inhibits sending data from the STM32W108C8 if not asserted The GPIO pins assigned to these signals are shown in Table 48. UART GPIO usage ...
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... SC1_UARTODD has no effect if SC1_UARTPAR is clear. 85/215 24 MHz = baud + Table 49 SC1_UARTPER SC1_UARTFRAC 40000 0 5000 0 2500 0 1250 0 625 0 312 1 208 1 104 Doc ID 018587 Rev 2 STM32W108C8 shows the values used to Baud rate error (%) 0.08 + 0.16 + 0.16 + 0.16 + 0.16 ...
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... STM32W108C8 A UART character frame contains, in sequence: ● The start bit ● The least significant data bit ● The remaining data bits ● If parity is enabled, the parity bit ● The stop bit, or bits stop bits are selected. Figure 10 shows the UART character frame format, with optional bits indicated. Depending on the options chosen for the character frame, the length of a character frame ranges from bit times ...
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... Flow control using RTS/CTS with software control of nRTS: nRTS controlled by SC1_UARTRTS bit in SC1_UARTCFG register Flow control using RTS/CTS with hardware control of nRTS: nRTS is asserted if room for at least 2 characters in receive FIFO Doc ID 018587 Rev 2 STM32W108C8 Other Device TXD UART Transmitter nCTS RXD ...
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... Direct memory access (DMA) channels The STM32W108C8 serial DMA channels enable efficient, high-speed operation of the SPI and UART controllers by reducing the load on the CPU as well as decreasing the frequency of interrupts that it must service. The transmit and receive DMA channels can transfer data between the transmit and receive FIFOs and the DMA buffers in main memory as quickly as it can be transmitted or received ...
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... Bits [1:0] SC_MODE: Serial controller mode. 0: Disabled. 1: UART mode (valid only for SC1). 89/215 0x0000 0000 Reserved Reserved Doc ID 018587 Rev 2 STM32W108C8 SPI mode mode SC_MODE rw ...
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... STM32W108C8 9.8.2 Serial controller interrupt flag register (INT_SCxFLAG) Address offset: 0xA808 (INT_SC1FLAG) and 0xA80C (INT_SC2FLAG) Reset value: Table 52. Serial controller interrupt flag register (INT_SCxFLAG INT_S INT_S INT_S INT_S C1PA C1FR CTXU CTXU Reser RERR MERR LDB LDA ...
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... Reserved INT_S INT_S INT_S INT_S INT_S CRXU CRXU CCMD CTXFI CNAK LDB LDA FIN interrupt enable. Doc ID 018587 Rev 2 STM32W108C8 INT_S INT_S INT_S INT_SC CTXU CRXO CTXID RXFIN ...
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... STM32W108C8 9.8.4 Serial controller interrupt mode register (SCx_INTMODE) Address offset: 0xA854 (SC1_INTMODE) and 0xA858 (SC2_INTMODE) Reset value: Table 54. Serial controller interrupt mode register (SCx_INTMODE Bit 2 SC_TXIDLELEVEL: Transmitter idle interrupt mode 0: Edge triggered Bit 1 SC_TXFREELEVEL: Transmit buffer free interrupt mode ...
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... Bit 0 SC_SPIPOL: Clock polarity configuration: clear this bit for a rising leading edge and set this bit for a falling leading edge. 93/215 0x0000 0000 Reserved Doc ID 018587 Rev 2 STM32W108C8 SC_S SC_SPI SC_SP SC_SP ...
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... STM32W108C8 9.9.3 SPI status register (SCx_SPISTAT) Address offset: 0xC840 (SC1_SPISTAT) and 0xC040 (SC2_SPISTAT) Reset value: Table 57. SPI status register (SCx_SPISTAT Bit 3 SC_SPITXIDLE: This bit is set when both the transmit FIFO and the transmit serializer are empty. Bit 2 SC_SPITXFREE: This bit is set when the transmit FIFO has space to accept at least one byte. ...
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... Reserved Reserved 2 C) interface registers 0x0000 0000 Reserved Reserved Doc ID 018587 Rev 2 STM32W108C8 SC_RATEEXP for a description of the SC_T SC_T WICM ...
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... STM32W108C8 2 9.11 control 1 register (SCx_TWICTRL1) Address offset: 0xC84C (SC1_TWICTRL1) and 0xC04C (SC2_TWICTRL1) Reset value: 2 Table 61 control 1 register (SCx_TWICTRL1 Bit 3 SC_TWISTOP: Setting this bit sends the STOP command. It clears when the command completes. Bit 2 SC_TWISTART: Setting this bit sends the START or repeated START command. It clears when the command completes ...
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... Bit 0 SC_UARTCTS: This bit is set when both the transmit FIFO and the transmit serializer are empty. 97/215 0x0000 0040 Reserved SC_UA RTTXI Doc ID 018587 Rev 2 STM32W108C8 SC_U SC_UA SC_UA SC_UA ARTF RTPAR ...
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... Bit 1 SC_UART8BIT: Number of data bits data bits. Bit 0 SC_UARTRTS: nRTS is an output to control the flow of serial data sent to the STM32W108C8 from another device. This bit directly controls the output at the nRTS pin (SC_UARTFLOW must be set and SC_UARTAUTO must be cleared). When this bit is set, nRTS is asserted (pin is low, 'XON', RS232 positive voltage) ...
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... Bits [0] SC_UARTFRAC: The fractional part of the baud rate period (F) in the equation: Rate = 24 MHz / ( ( 99/215 0x0000 0000 Reserved SC_UARTPER rw 0x0000 0000 Reserved Reserved Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 9.13 DMA channel registers 9.13.1 Serial DMA control register (SCx_DMACTRL) Address offset: 0xC830 (SC1_DMACTRL) and 0xC030 (SC2_DMACTRL) Reset value: Table 67. Serial DMA control register (SCx_DMACTRL Reserved Bit 5 SC_TXDMARST: Setting this bit resets the transmit DMA. The bit clears automatically. ...
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... Bit 3 This bit is set when DMA transmit buffer B is active. 101/215 0x0000 0000 Reserved SC_RX SC_RX SC_RX SC_RX FRMB FRMA PARB PARA Doc ID 018587 Rev 2 STM32W108C8 SC_RX SC_R SC_TX SC_TX OVFB XOVF ACTB ACTA ...
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... STM32W108C8 Bit 2 This bit is set when DMA transmit buffer A is active. Bit 1 This bit is set when DMA receive buffer B is active. Bit 0 This bit is set when DMA receive buffer A is active. 9.13.3 Transmit DMA begin address register A (SCx_TXBEGA) Address offset: 0xC810 (SC1_TXBEGA) and 0xC010 (SC2_TXBEGA) Reset value: Table 69 ...
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... Reserved SC_TXENDA 0x2000 0000 Reserved SC_TXENDB 0x0000 0000 Reserved SC_TXCNT Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Bits [12:0] SC_TXCNT: The offset from the start of the active DMA transmit buffer from which the next byte will be read. This register is set to zero when the buffer is loaded and when the DMA is reset. 9.13.8 Receive DMA begin address register A (SCx_RXBEGA) Address offset: 0xC800 (SC1_RXBEGA) and 0xC000 (SC2_RXBEGA) Reset value: Table 74 ...
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... Bits [12:0] SC_RXENDB: Address of the last byte that will be written in the DMA receive buffer B. 105/215 0x0000 0000 Reserved SC_RXENDA 0x2000 0000 Reserved SC_RXENDB Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 9.13.12 Receive DMA count register A (SCx_RXCNTA) Address offset: 0xC820 (SC1_RXCNTA) and 0xC020 (SC2_RXCNTA) Reset value: Table 78. Receive DMA count register A (SCx_RXCNTA Reserved Bits [12:0] SC_RXCNTA: The offset from the start of DMA receive buffer A at which the next byte will be written ...
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... DMA is reset. 107/215 0x0000 0000 Reserved SC_RXCNTSAVED 0x0000 0000 Reserved SC_RXERRA Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 9.13.16 DMA first receive error register B (SCx_RXERRB) Address offset: 0xC838 (SC1_RXERRB) and 0xC038 (SC2_RXERRB) Reset value: Table 82. DMA first receive error register B (SCx_RXERRB Reserved Bits [12:0] SC_RXERRB: The offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error ...
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... General-purpose timers 10 General-purpose timers Each of the STM32W108C8's two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler ...
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... Functional description The timers can optionally use GPIOs in the PA and PB ports for external inputs or outputs. As with all STM32W108C8 digital inputs, a GPIO used as a timer input can be shared with other uses of the same pin. Available timer inputs include an external timer clock, a clock mask, and four input channels ...
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... TIMxC1 TIMxC2 TIMxC3 (in or out) (in or out) (in or out) PB6 PB7 PA6 PA0 PA3 PA1 PB1 PB2 PB3 Doc ID 018587 Rev 2 STM32W108C8 Table 83. The Timer 2 Option TIMxC4 TIMxCLK TIMxMSK (in or out) (in) (in) PA7 PB0 PB5 PA2 PB5 PB0 PB4 PB5 ...
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... STM32W108C8 Note: When the STM32W108C8 enters debug mode and the ARM® Cortex-M3 core is halted, the counters continue to run normally. Prescaler The prescaler can divide the counter clock frequency by power of two from 1 through 32768 based on a 16-bit counter controlled through the 4-bit TIM_PSCEXP bit field in the TIMx_PSC register ...
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... The auto-reload shadow register is updated with the buffer value (TIMx_ARR). Figure 15, Figure behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 15. Counter timing diagram, internal clock divided by 1 Figure 16. Counter timing diagram, internal clock divided by 4 113/215 16, Figure 17, and Figure 18 show some examples of the counter Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Figure 17. Counter timing diagram, update event when TIM_ARBE = 0 (TIMx_ARR not buffered) Figure 18. Counter timing diagram, update event when TIM_ARBE = 1 (TIMx_ARR buffered) Down-counting mode In down-counting mode, the counter counts from the auto-reload value (contents of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event ...
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... Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register and generates a counter overflow event, then counts from the 115/215 show some examples of the counter behavior for different clock Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. In this mode, the direction bit (TIM_DIR in the TIMx_CR1 register) cannot be written updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow ...
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... General-purpose timers Figure 22. Counter timing diagram, update event with TIM_ARBE = 1 (counter underflow) Figure 23. Counter timing diagram, update event with TIM_ARBE = 1 (counter overflow) 117/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 10.1.3 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (PCLK) ● External clock mode 1: external input pin (TIy) ● External clock mode 2: external trigger input (ETR) ● Internal trigger input (ITR0): using the other timer as prescaler. Refer to the ...
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... When a rising edge occurs on TI2, the counter counts once and the INT_TIMTIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on the TI2 input. Figure 26. Control circuit in External Clock mode 1 119/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 External clock source mode 2 This mode is selected by writing TIM_ECE = 1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The TIM_EXTRIGSEL bits in the TIMx_OR register select a clock signal that drives ETR, as shown in Table 84 ...
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... Figure 29. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate reference signal, OCyREF, which is only used internally. OCyREF is always active high, but it may be inverted to create the output signal, OCy, that controls a GPIO output. 121/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Figure 30. Capture/compare channel 1 main circuit Figure 31. Output stage of capture/compare channel (channel 1) The capture/compare block is made of a buffer register and a shadow register. Writes and reads always access the buffer register. In capture mode, captures are first written to the shadow register, then copied into the buffer register ...
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... Two ICy signals are mapped on the same TIy input. ● These two ICy signals are active on edges with opposite polarity. ● One of the two TIyFP signals is selected as trigger input and the slave mode controller is configured in reset mode. 123/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 For example, to measure the period in the TIMx_CCR1 register and the duty cycle in the TIMx_CCR2 register of the PWM applied on TI1, use the following procedure depending on CK_INT frequency and prescaler value: ● Select the active input for TIMx_CCR1: write the TIM_CC1S bits the TIMx_CCMR1 register (TI1 selected). ● ...
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... To control the output waveform, software can update the TIMx_CCRy register at any time, provided that the buffer register is not enabled (TIM_OCyBE = 0). Otherwise TIMx_CCRy shadow register is updated only at the next update event. An example is given in 125/215 Section 10.1.8: Output compare mode on page Doc ID 018587 Rev 2 STM32W108C8 125. Figure 33. ...
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... STM32W108C8 Figure 33. Output compare mode, toggle on OC1 10.1.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register, and a duty cycle determined by the value of the TIMx_CCRy register. PWM mode can be selected independently on each channel (one PWM per OCy output) by writing 110 (PWM mode 1) or 111 (PWM mode 2) in the TIM_OCyM bits in the TIMx_CCMR1 register ...
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... TIM_CMS bits configuration. The direction bit (TIM_DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to more information. 127/215 112. Figure 34 for more information. Center-aligned mode (up/down counting) on page 115 Doc ID 018587 Rev 2 STM32W108C8 Up- shows some edge-aligned for ...
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... STM32W108C8 Figure 35 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR = 8, ● PWM mode is the PWM mode 1, ● The output compare flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for TIM_CMS = 01 in the TIMx_CR1 register. Figure 35. Center-aligned PWM waveforms (ARR = 8) Hints on using center-aligned mode: ● ...
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... A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: In up-counting: TIMx_CNT < TIMx_CCRy ≤ TIMx_ARR (in particular, 0 < TIMx_CCRy), ● ● In down-counting: TIMx_CNT > TIMx_CCRy. Figure 36. Example of one pulse mode 129/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 For example, to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a rising edge is detected on the TI2 input pin, using TI2FP2 as trigger 1: ● Map TI2FP2 on TI2 by writing TIM_IC2S = 01 in the TIMx_CCMR1 register. ● TI2FP2 must detect a rising edge. Write TIM_CC2P = 0 in the TIMx_CCER register. ...
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... TIM_CEN = 1 (TIMx_CR1 register, counter is enabled). 131/215 TI1FP1 signal Rising TI1) High Down Low Up High No Count No Count Low No Count No Count High Down Low Up Doc ID 018587 Rev 2 STM32W108C8 TI2FP2 signal Falling Rising Up No Count No Count Down No Count No Count Up Down Up Up Down Down Table 85 Falling Down Up ...
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... STM32W108C8 Figure 37. Example of counter operation in encoder interface mode Figure 38 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except TIM_CC1P = 1). Figure 38. Example of encoder interface mode with IC1FP1 polarity inverted The timer configured in encoder interface mode provides information on a sensor's current position ...
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... Figure 39 shows this behavior when the auto-reload register TIMx_ARR = 0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on the TI1 input. Figure 39. Control circuit in Reset mode 133/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Slave mode: Gated mode In Gated mode the counter is enabled depending on the level of a selected input. In the following example, the up-counter counts only when the TI1 input is low: ● Configure channel 1 to detect low levels on TI1 Configure the input filter duration. In this example, no filter is required, so TIM_IC1F = 0000 ...
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... A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. 135/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Figure 42. Control circuit in External clock mode 2 + Trigger mode 10.1.14 Timer synchronization The two timers can be linked together internally for timer synchronization or chaining. A timer configured in Master mode can reset, start, stop or clock the counter of the other timer configured in Slave mode. Figure 43 presents an overview of the trigger selection and the master mode selection blocks ...
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... Configure Timer 2 in gated mode (TIM_SMS = 101 in the TIM2_SMCR register). ● Reset Timer 1 by writing 1 in the TIM_UG bit (TIM1_EGR register). 137/215 for connections. Timer 2 counts on the divided internal clock only when Figure 44, the Timer 2 counter and prescaler are not initialized before Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 ● Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register). ● Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL). ● Enable Timer 2 by writing 1 in the TIM_CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing 1 in the TIM_CEN bit (TIM1_CR1 register). ...
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... Configure Timer 1 slave mode to get the input trigger from TI1 (TIM_TS = 100 in the TIM1_SMCR register). ● Configure Timer 1 in trigger mode (TIM_SMS = 110 in the TIM1_SMCR register). 139/215 Figure 43 for connections. To ensure the counters are Doc ID 018587 Rev 2 STM32W108C8 Figure 46, but in trigger ...
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... Timer signal descriptions Signal CK_INT CK_PSC ETR ETRF ETRP ICy Internal/external Internal clock source: connects to STM32W108C8 peripheral Internal clock (PCLK) in internal clock mode. Internal Input to the clock prescaler. External trigger input (used in external timer mode 2): a clock Internal selected by TIM_EXTRIGSEL in TIMx_OR. Internal External trigger: ETRP after filtering ...
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... Timer channel at a GPIO pin: can be a capture input (ICy) or Internal a compare output (OCy). External Clock input (if selected) to the external trigger signal (ETR). Clock mask (if enabled) AND'ed with the other timer's External TIMxCLK signal. Internal Trigger input for slave mode controller. Doc ID 018587 Rev 2 STM32W108C8 Description Section 12: Interrupts ...
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... STM32W108C8 10.3 General-purpose timer (1 and 2) registers 10.3.1 Timer x control register 1 (TIMx_CR1) Address offset: 0xE000 (TIM1) and 0xF000 (TIM2) Reset value: Table 87. Timer x control register 1 (TIMx_CR1 Reserved Bit 7 TIM_ARBE: Auto-Reload Buffer Enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. ...
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... Bit 7 TIM_TI1S: TI1 Selection 0: TI1M (input of the digital filter) is connected to TI1 input. 1: TI1M is connected to the TI_HALL inputs (XOR combination). 143/215 0x0000 0000 Reserved TIM_TI 1S rw Doc ID 018587 Rev 2 STM32W108C8 TIM_MMS Reserved ...
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... STM32W108C8 Bits [6:4] TIM_MMS: Master Mode Selection This selects the information to be sent in master mode to a slave timer for synchronization using the trigger output (TRGO). 000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output. If the reset is generated by the trigger input (slave mode controller configured in reset mode), then the signal on TRGO is delayed compared to the actual reset ...
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... Sampling 0110: f Sampling 0111: f Sampling Note: PCLK is 12 MHz when the STM32W108C8 is using the 24 MHz crystal oscillator, and 6 MHz if using the 12 MHz RC oscillator. Bit 7 TIM_MSM: Master/Slave Mode 0: No action. 1: The effect of an event on the trigger input (TRGI) is delayed to allow exact synchronization between the current timer and the slave (through TRGO) ...
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... STM32W108C8 Bits [2:0] TIM_SMS: Slave Mode Selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. If TIM_CEN = 1 then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1. Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. ...
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... Re-initializes the counter and generates an update of the registers. This also clears the prescaler counter but the prescaler ratio is not affected. The counter is cleared if center-aligned mode is selected or if TIM_DIR=0 (up-counting), otherwise it takes the auto-reload value (TMR1_ARR) if TIM_DIR=1 (down-counting). 147/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 10.3.5 Timer x capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0xE018 (TIM1) and 0xF018 (TIM2) Reset value: Table 91. Timer x capture/compare mode register 1 (TIMx_CCMR1 TIM_O TIM_OC2M C2BE TIM_IC2F TIM_IC2PSC Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). ...
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... Bits [7:4] TIM_IC1F: Input Capture 1 Filter. (Applies only if TIM_CC1S > 0) See TIM_IC2F description above. Bits [3:2] TIM_IC1PSC: Input Capture 1 Prescaler. (Applies only if TIM_CC1S > 0) See TIM_IC2PSC description above. 149/215 1000: Fsampling=PCLK/8, N=6. 1001: Fsampling=PCLK/8, N=8. 1010: Fsampling=PCLK/16, N=5. 1011: Fsampling=PCLK/16, N=6. 1100: Fsampling=PCLK/16, N=8. 1101: Fsampling=PCLK/32, N=5. 1110: Fsampling=PCLK/32, N=6. 1111: Fsampling=PCLK/32, N=8. Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Bits [1:0] TIM_CC1S: Capture / Compare 1 Selection This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is mapped to TI1. 10: Channel is an input and is mapped to TI2. 11: Channel is an input and is mapped to TRGI. This requires an internal trigger input selected by the TIM_TS bit in the TIM_SMCR register ...
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... An active edge on the trigger input acts like a compare match on the OC4 output. OC4 is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate OC4 output is reduced to 3 clock cycles. TIM_OC4FE acts only if the channel is configured in PWM 1 or PWM 2 mode. 151/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Bits [15:12] TIM_IC4F: Input Capture 1 Filter. (Applies only if TIM_CC4S > 0) This defines the frequency used to sample the TI4 input, f filter applied to TI4. The digital filter requires N consecutive samples in the same state before being output. 0000: f Sampling 0001: f Sampling 0010: f Sampling 0011: f ...
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... Refer to the CC4P description above. Bit 8 TIM_CC3E Refer to the CC4E description above. 153/215 0x0000 0000 Reserved TIM_C TIM_C C3P C3P Reserved rw rw Doc ID 018587 Rev 2 STM32W108C8 TIM_C TIM_C C2P C2P Reserved ...
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... STM32W108C8 Bit 5 TIM_CC2P Refer to the CC4P description above. Bit 4 TIM_CC2E Refer to the CC43 description above. Bit 1 TIM_CC1P Refer to the CC4P description above. Bit 0 TIM_CC1E Refer to the CC4E description above. 10.3.8 Timer x counter register (TIMx_CNT) Address offset: 0xE024 (TIM1) and 0xF024 (TIM2) Reset value: Table 94 ...
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... CCR1 is the counter value transferred by the last input capture 1 event (IC1). 155/215 0x0000 0000 Reserved TIM_ARR rw 0x0000 0000 Reserved TIM_CCR rw Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 10.3.12 Timer x capture/compare 2 register (TIMx_CCR2) Address offset: 0xE038 (TIM1) and 0xF038 (TIM2) Reset value: Table 98. Timer x capture/compare 2 register (TIMx_CCR2 Bits [15:0] See description in the TIMx_CCR1 register. 10.3.13 Timer x capture/compare 3 register (TIMx_CCR3) Address offset: 0xE03C (TIM1) and 0xF03C (TIM2) Reset value: Table 99 ...
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... Reserved Reserved 0x0000 0000 Reserved TIM_R TIM_R EMAP EMAP C4 rw Doc ID 018587 Rev 2 STM32W108C8 TIM_O TIM_C RRSV LKMS D KEN TIM_R ...
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... STM32W108C8 Bit 3 TIM_ORRSVD Reserved: this bit must always be set to 0. Bit 2 TIM_CLKMSKEN Enables TIM2MSK when TIM2CLK is selected as the external trigger TIM2MSK not used TIM2CLK is ANDed with the TIM2MSK input. Bits [1:0] TIM1_EXTRIGSEL Selects the external trigger used in external clock mode PCLK calibrated 1 kHz clock kHz reference clock (if available TIM2CLK pin ...
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... Bit 9 INT_TIMMISSCC1IF: Capture or compare 1 interrupt missed. Bits [6:0] INT_TIMMISSRSVD: May change during normal operation. 159/215 0x0000 0000 Reserved INT_TI INT_TI MMIS MMISS SCC2I Reserved CC1IF Doc ID 018587 Rev 2 STM32W108C8 INT_TIMMISSRSVD ...
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... STM32W108C8 11 Analog-to-digital converter The STM32W108C8 analog-to-digital converter (ADC first-order sigma-delta converter with the following features: ● Resolution bits ● Sample times as fast as 5.33 µs (188 kHz) ● Differential and single-ended conversions from six external and four internal sources ● ...
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... PB0. If internally generated, it may optionally be output on PB0. To use an external reference system function must be called after reset and after waking from deep sleep. PB0 must also be configured in analog mode using GPIO_PBCFGH[3:0]. See the STM32W108C8 HAL documentation for more information on the system functions required to use an external reference. 161/215 ...
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... STM32W108C8 11.1.4 Offset/gain correction When a conversion is complete, the 16-bit converted data is processed by offset/gain correction logic: ● The basic ADC conversion result is added to the 16-bit signed (two’s complement) value of the ADC offset register (ADC_OFFSET). ● The offset-corrected data is multiplied by the 16-bit ADC gain register, ADC_GAIN, to produce a 16-bit signed result ...
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... Internal connection Calibration 1V8 VREG/2 Internal connection Supply monitoring and calibration No connection No connection No connection No connection ADC N input ADC_MUXP VREF/2 VREF/2 VREF/2 VREF/2 VREF/2 VREF/2 ADC0 ADC2 Doc ID 018587 Rev 2 STM32W108C8 Purpose ADC_MUXN 0 9 Single-ended 1 9 Single-ended 2 9 Single-ended 3 9 Single-ended 4 9 Single-ended ...
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... STM32W108C8 Table 108. Typical ADC input configurations (continued) ADC P input ADC5 GND VREF VDD_PADSA/2 Input range ADC inputs can be routed through input buffers to expand the input voltage range. The input buffers have a fixed 0.25 gain and the converted data is scaled by that factor. ...
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... ADC_PERIOD clocks 6 7 Note: ADC sample timing is the same whether the STM32W108C8 is using the 24 MHz crystal oscillator or the 12 MHz high-speed RC oscillator. This facilitates using the ADC soon after the CPU wakes from deep sleep, before switching to the crystal oscillator. 11.1.7 Operation Setting the ADC_EN bit in the ADC_CFG register enables the ADC; once enabled, it performs conversions continuously until it is disabled. If the ADC had previously been disabled µ ...
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... STM32W108C8 To convert multiple inputs using this approach, repeat Steps 4 through 6, loading the desired input configurations to ADC_CFG in Step 5. If the inputs can use the same offset/gain correction, just repeat Steps 5 and 6. 11.1.8 Calibration Sampling of internal connections GND, VREF/2, and VREF allow for offset and gain calibration of the ADC in applications where absolute accuracy is important ...
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... INT_ADCOVF flag immediately after enabling the DMA, preferably with interrupts off. Disabling the ADC in addition to the DMA is often undesirable because of the additional analog startup time when it is re-enabled. 167/215 ® Cortex-M3 vectored interrupt with programmable priority. The Doc ID 018587 Rev 2 STM32W108C8 Section 12: Interrupts on ...
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... STM32W108C8 11.3 Analog-to-digital converter (ADC) registers 11.3.1 ADC configuration register (ADC_CFG) Address offset: 0xD004 Reset value: Table 111. ADC configuration register (ADC_CFG ADC_ ADC_ ADC_PERIOD HVSE HVSE Bits [15:13] ADC_PERIOD: ADC sample time in clocks and the equivalent significant bits in the conversion. ...
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... It can represent values from 0 to (almost) 2. The reset value is a gain factor of 1. 169/215 0x0000 0000 Reserved ADC_OFFSET_FIELD rw 0x0000 8000 Reserved ADC_GAIN_FIELD rw Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 11.3.4 ADC DMA configuration register (ADC_DMACFG) Address offset: 0xD010 Reset value: Table 114. ADC DMA configuration register (ADC_DMACFG Bit 4 ADC_DMARST: Write 1 to reset the ADC DMA. This bit auto-clears. Bit 1 ADC_DMAAUTOWRAP: Selects DMA mode. 0: Linear mode, the DMA stops when the buffer is full. ...
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... Reserved ADC_DMABEG 0x0000 0000 Reserved ADC_DMASIZE_FIELD 0x2000 0000 Reserved Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Table 118. ADC DMA current address register (ADC_DMACUR) (continued) Reserved Bits [12:1] ADC_DMACUR_FIELD: Current DMA address: the location that will be written next by the DMA. 11.3.9 ADC DMA count register (ADC_DMACNT) Address offset: 0xD024 Reset value: Table 119. ADC DMA count register (ADC_DMACNT) ...
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... Bit 0 ST Reserved: this bit must always be set to 0. 173/215 0x0000 0000 Reserved Reserved 0x0000 0000 Reserved Reserved Doc ID 018587 Rev 2 STM32W108C8 INT_A INT_A INT_A DCOV DCUL DCSAT F DFULL ...
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... STM32W108C8 12 Interrupts The STM32W108C8's interrupt system is composed of two parts: a standard ARM® Cortex- M3 Nested Vectored Interrupt Controller (NVIC) that provides top level interrupts, and an Event Manager (EM) that provides second level interrupts. The NVIC and EM provide a simple hierarchy. All second level interrupts from the EM feed into top level interrupts in the NVIC ...
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... Sleep Timer peripheral interrupt. 21 Serial Controller 1 peripheral interrupt. 22 Serial Controller 2 peripheral interrupt. 23 Security peripheral interrupt. 24 MAC Timer peripheral interrupt. 25 MAC Transmit peripheral interrupt. 26 MAC Receive peripheral interrupt. 27 ADC peripheral interrupt. 28 IRQA peripheral interrupt. 29 IRQB peripheral interrupt. 30 IRQC peripheral interrupt. Doc ID 018587 Rev 2 STM32W108C8 Description ...
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... The NMI has two second-level sources; failure of the 24 MHz crystal and watchdog low water mark. 1. Failure of the 24 MHz crystal: If the STM32W108C8's main clock, SCLK, is operating from the 24 MHz crystal and the crystal fails, the STM32W108C8 detects the failure and automatically switch to the internal 12 MHz RC clock. When this failure detection Position 31 IRQD peripheral interrupt ...
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... Usage Fault. Of these four, three of the faults (Hard Fault, Memory Fault, and Usage Fault) are all standard ARM® Cortex-M3 exceptions. The Bus Fault, though, is derived from STM32W108C8-specific sources. The Bus Fault sources are recorded in the SCS_AFSR register. Note that it is possible for one access to set multiple SCS_AFSR bits ...
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... STM32W108C8 Figure 50. Peripheral interrupts block diagram peripheral interrupt instance OR AND S source interrupt events The description of each peripheral's interrupt configuration and flag registers can be found in the chapters of this datasheet describing each peripheral. Given a peripheral, 'periph', the Event Manager registers (INT_periphCFG and INT_periphFLAG) follow the form: ● ...
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... INT_periphFLAG register-by writing a 1 into the corresponding bit to be cleared. Table 123 provides a map of all peripheral interrupts. This map lists the top level NVIC Interrupt bits and, if there is one, the corresponding second level EM Interrupt register bits that feed the top level interrupts. 179/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 Table 123. NVIC and EM peripheral interrupt map NVIC Interrupt (top level) 16 INT_DEBUG 15 INT_IRQD 14 INT_IRQC 13 INT_IRQB 12 INT_IRQA 11 INT_ADC 10 INT_MACRX 9 INT_MACTX 8 INT_MACTMR 7 INT_SEC 6 INT_SC2 EM Interrupt (second level) 5 INT_SC1 INT_ADCFLAG register 4 INT_ADCOVF 3 INT_ADCSAT 2 INT_ADCULDFULL 1 INT_ADCULDHALF 0 INT_ADCDATA INT_SC2FLAG register 12 INT_SCTXULDB 4 INT_SLEEPTMR 11 INT_SCTXULDA 3 INT_BB 10 INT_SCRXULDB ...
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... Bit 0 INT_TIM1: Write 1 to enable timer 1 interrupt. (Writing 0 has no effect.) 181/215 0xE000E100 0x0000 0000 Reserved INT_M INT_M INT_M INT_S ACTM ACRX ACTX Doc ID 018587 Rev 2 STM32W108C8 INT_S INT_S INT_S INT_B INT_M LEEPT GMT ...
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... STM32W108C8 12.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) Address: 0xE000E180 Reset value: Table 125. Top-level clear interrupts configuration register (INT_CFGCLR INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA Bit 16 INT_DEBUG: Write 1 to disable debug interrupt. (Writing 0 has no effect.) Bit 15 INT_IRQD: Write 1 to disable IRQD interrupt ...
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... Bit 0 INT_TIM1: Write 1 to pend timer 1 interrupt. (Writing 0 has no effect.) 183/215 0x0000 0000 Reserved INT_M INT_M INT_M INT_S INT_S ACTM ACRX ACTX Doc ID 018587 Rev 2 STM32W108C8 INT_S INT_SC INT_B INT_M LEEP GMT TMR ...
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... STM32W108C8 12.3.4 Top-level clear interrupts pending register (INT_PENDCLR) Address: 0xE000E280 Reset value: Table 127. Top-level clear interrupts pending register (INT_PENDCLR INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA Bit 16 INT_DEBUG: Write 1 to unpend debug interrupt. (Writing 0 has no effect.) Bit 15 INT_IRQD: Write 1 to unpend IRQD interrupt ...
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... Bit 0 INT_TIM1: Timer 1 interrupt active. 185/215 0x0000 0000 Reserved INT_M INT_M INT_M INT_S INT_S ACTM ACRX ACTX Doc ID 018587 Rev 2 STM32W108C8 INT_S INT_SC INT_B INT_M LEEP GMT TMR ...
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... STM32W108C8 12.3.6 Top-level missed interrupts register (INT_MISS) Address: 0x4000 A820 Reset value: Table 129. Top-level missed interrupts register (INT_MISS INT_M INT_M INT_M INT_M INT_M ISSIR ISSIR ISSIR ISSIR ISSAD Bit 15 INT_MISSIRQD: IRQD interrupt missed. ...
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... RAM or flash. Bit 0 MISSED A bus fault occurred when a bit was already set in this register. 187/215 0xE000ED3C 0x0000 0000 Reserved Reserved Doc ID 018587 Rev 2 STM32W108C8 WRON PROT GSIZE ECTE D rw ...
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... STM32W108C8 13 Debug support The STM32W108C8 includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug and programming interface of the STM32W108C8. The SWJ gives debug tools access to the internal buses of the STM32W108C8, and allows for non-intrusive memory and register access as well as CPU halt-step style debugging. Therefore, any design implementing the STM32W108C8 should make the SWJ signals readily available. Serial Wire is an ARM® ...
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... For each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in the data scan chain. Note: Important: Once Serial-Wire is selected using the dedicated ARM JTAG sequence, the TMC TAP is automatically disabled (JTMS forced high). 189/215 Doc ID 018587 Rev 2 STM32W108C8 ...
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... STM32W108C8 14 Electrical characteristics 14.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 14.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range) ...
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... T J 191/215 characteristics, and Table 133: Thermal characteristics Ratings characteristics) Ratings /V power lines (source) DD DDA ground lines (sink) SS Ratings Storage temperature range Maximum junction temperature Doc ID 018587 Rev 2 STM32W108C8 Table 131: Voltage characteristics, may cause Min. Max. -0.3 +3.6 -0.3 +2.0 -0.3 +3.6 – +15 -0.3 VDD_PADS +0.3 -0.3 VDD_PADSA +0.3 Max. ...
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... Operating conditions at power-up Power-on resets (POR HV and POR LV) The STM32W108C8 measures the voltage levels supplied to the three power domains supply voltage drops below a low threshold, then a reset is applied. The reset is released if the supply voltage rises above a high threshold. There are three detection circuits for power on reset as follows: ● ...
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... MSL Moisture sensitivity level 1. Based on characterization results, not tested in production. 193/215 Parameter Ratings Conditions = +25 ° compliance with JESD22-A114 = +25 ° compliance with JESD22-A114 – Doc ID 018587 Rev 2 STM32W108C8 Min Typ Max Unit 2.1 12.0 16.0 µs 26.0 – – µs 0 – 1.0 µs (1) Class Maximum value ...
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... STM32W108C8 Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. ...
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... V p-p swing) and a Nyquist ( 5.33 10.7 21.3 93.8 46.9 23.4 56.6 28.3 14.1 0.084 0.084 0.15 0.046 0.044 0.076 0.026 0.023 0.044 0.007 0.009 0.013 5.6 7.0 8 Doc ID 018587 Rev 2 STM32W108C8 (1) (continued) Performance -67 -69 -69 -69 -71 -75 -76 -76 10.0 11.3 12.2 12.4 10.1 11.4 12.5 12.9 9.9 10.9 11.2 11.3 10.0 11.3 12.1 12 [15:6] [15:5] [15:4] [15:3] Table 141. = 7.7% f input Performance 3 4 ...
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... STM32W108C8 Table 142. ADC module key parameters for input buffer disabled and 6 MHz sampling Parameter SDFR (dB) Single-Ended Differential THD (dB) Single-Ended Differential ENOB (from SNR) Single-Ended Differential ENOB (from SINAD) Single-Ended Differential Equivalent ADC Bits 1. INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of ENOB (effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or SINAD (signal-to-noise and distortion ratio) ...
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... Doc ID 018587 Rev 2 STM32W108C8 = 7.7% f input Performance 256 512 1024 2048 11.7 5.86 2.93 1.47 7.07 3.54 1.77k 0.884 0.07 0.123 0.261 0.522 0.04 0.077 0.167 0.326 0.04 0.077 0.167 0.326 0.007 0.008 0.013 0.023 8.1 9.5 10.7 11 ...
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... STM32W108C8 Table 144 lists other specifications for the ADC not covered in Table 143. Table 144. ADC characteristics Parameter VREF VREF output current VREF load capacitance External VREF voltage range External VREF input impedance Minimum input voltage Input buffer disabled Input buffer enabled ...
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... Min. – – – – – – – – – – – – – – – – Test conditions Min. After trimming – Doc ID 018587 Rev 2 STM32W108C8 Min. Typ. Max. Unit MHz 0.5 MHz Typ. Max. Unit – 24 – MHz -40 – ...