STM8S105S4 STMicroelectronics, STM8S105S4 Datasheet - Page 96

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STM8S105S4

Manufacturer Part Number
STM8S105S4
Description
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S105S4

Ram
Up to 2 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization
Two Watchdog Timers
Window watchdog and independent watchdog

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Electrical characteristics
96/127
Symbol
t
t
t
t
C
(1)
(2)
(3)
low time.
(4)
the undefined region of the falling edge of SCL.
w(STO:STA)
h(STA)
su(STA)
su(STO)
b
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
f
Data based on standard I
The maximum hold time of the start condition has only to be met if the interface does not stretch the
MASTER
, must be at least 8 MHz to achieve max fast I
Parameter
START condition hold time
Repeated START condition
setup time
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
1. Measurement points are made at CMOS levels: 0.3 x V
Figure 44: Typical application with I
t f(SDA)
SDA
SCL
I²C bus
t w(SCLH)
2
C protocol requirement, not tested in production.
S TART
t h(STA)
V DD
t r(SDA)
DocID14771 Rev 10
t r(SCL)
t w(SCLL)
V DD
Standard mode I
Min
4.0
4.7
4.0
4.7
t su(SDA)
(2)
2
C speed (400kHz).
t f(SCL)
t h(SDA)
Max
2
400
C bus and timing diagram
SCL
SDA
(2)
2
t su(STA)
C
DD
STM8S105xx
Fast mode I
Min
0.6
0.6
0.6
1.3
S TOP
S TART REPEATED
and 0.7 x V
(2)
t su(STO)
Max
400
t su(STA:STO)
2
DD
C
S TART
(1)
(2)
ai15385b
STM8S105xx
(1)
Unit
μs
μs
μs
μs
pF

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