STM8AF528A

Manufacturer Part NumberSTM8AF528A
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF528A datasheet
 


Specifications of STM8AF528A

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
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STM8AF51xx STM8AF6169/7x/8x/9x/Ax
Automotive 8-bit MCU, with up to 128 Kbytes Flash, data EEPROM,
10-bit ADC, timers, LIN, CAN, USART, SPI, I
Features
Core
– Max f
: 24 MHz
CPU
– Advanced STM8A core with Harvard
architecture and 3-stage pipeline
– Average 1.6 cycles/instruction resulting in
10 MIPS at 16 MHz f
CPU
standard benchmark
Memories
– Program memory: 32 to 128 Kbytes Flash
program; data retention 20 years at 55 °C
– Data memory: up to 2 Kbytes true data
EEPROM; endurance 300 kcycles
– RAM: 2 Kbytes to 6 Kbytes
Clock management
– Low-power crystal resonator oscillator with
external clock input
– Internal, user-trimmable 16 MHz RC and
low-power 128 kHz RC oscillators
– Clock security system with clock monitor
Reset and supply management
– Wait/auto-wakeup/Halt low-power modes
with user definable clock gating
– Low consumption power-on and power-
down reset
Interrupt management
– Nested interrupt controller with 32 vectors
– Up to 37 external interrupts on 5 vectors
Timers
– 2 general purpose 16-bit timers with up to 3
CAPCOM channels each (IC, OC, PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization
– 8-bit AR basic timer with 8-bit prescaler
– Auto-wakeup timer
– Window and independent watchdog timers
I/Os
– Up to 68 user pins (11 high sink I/Os)
– Highly robust I/O design, immune against
current injection
February 2011
STM8AF52xx STM8AF6269/8x/Ax
for industry
Communication interfaces
– High speed 1 Mbit/s CAN 2.0B interface
– USART with clock output for synchronous
operation - LIN master mode
– LINUART LIN 2.1 compliant, master/slave
modes with automatic resynchronization
– SPI interface up to 10 Mbit/s or f
– I
Analog to digital converter (ADC)
– 10-bit resolution, 2 LSB TUE, 1 LSB
linearity and up to 16 multiplexed channels
Operating temperature up to 150 °C
Qualification conforms to
Table 1.
Part numbers: STM8AF52xx (with CAN)
STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A,
STM8AF5289, STM8AF5288, STM8AF5269, STM8AF5268
Part numbers: STM8AF6269/8x/Ax
STM8AF62AA, STM8AF62A9, STM8AF62A8, STM8AF628A,
STM8AF6289, STM8AF6288, STM8AF6286, STM8AF6269
Part numbers: STM8AF51xx (with CAN)
STM8AF51AA, STM8AF51A9, STM8AF51A8, STM8AF519A,
STM8AF5199, STM8AF5198, STM8AF518A, STM8AF5189,
STM8AF5188, STM8AF5179, STM8AF5178, STM8AF5169,
STM8AF5168
Part numbers: STM8AF6169/7x/8x/9x/Ax
STM8AF61AA, STM8AF61A9, STM8AF61A8, STM8AF619A,
STM8AF6199, STM8AF6198, STM8AF618A, STM8AF6189,
STM8AF6188, STM8AF6186, STM8AF6179, STM8AF6178,
STM8AF6176, STM8AF6169
1.
In the order code, the letter ‘F’ applies to devices featuring
Flash and data EEPROM. ‘F’ is replaced by ‘H’ for devices
with Flash only, and by ‘P’ for devices with FASTROM (see
Table
Doc ID 14395 Rev 8
2
C, 3 to 5.5 V
LQFP48 7x7
LQFP80 14x14
LQFP64 10x10
LQFP32 7x7
2
C interface up to 400 Kbit/s
AEC-Q100 rev G
(1)
Device summary
2,
Table
4,
Table
3,
Table
5, and
Figure
48).
/2
MASTER
1/106
www.st.com
1

STM8AF528A Summary of contents

  • Page 1

    ... Operating temperature up to 150 °C ■ Qualification conforms to Table 1. Part numbers: STM8AF52xx (with CAN) STM8AF52AA, STM8AF52A9, STM8AF52A8, STM8AF528A, STM8AF5289, STM8AF5288, STM8AF5269, STM8AF5268 Part numbers: STM8AF6269/8x/Ax STM8AF62AA, STM8AF62A9, STM8AF62A8, STM8AF628A, STM8AF6289, STM8AF6288, STM8AF6286, STM8AF6269 Part numbers: STM8AF51xx (with CAN) STM8AF51AA, STM8AF51A9, STM8AF51A8, STM8AF519A, ...

  • Page 2

    Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    STM8AF52/62xx, STM8AF51/61xx 5.7.4 5.7.5 5.8 Analog to digital converter (ADC ...

  • Page 4

    Contents 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.3.10 I 10.3.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    STM8AF52/62xx, STM8AF51/61xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    List of tables Table 47. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 7

    STM8AF52/62xx, STM8AF51/61xx List of figures Figure 1. STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 8

    Introduction 1 Introduction This datasheet refers to the STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx products with 32 to 128 Kbytes of program memory. In the order code, the letter ‘F’ refers to product versions with Flash and data EEPROM, ‘H’ to ...

  • Page 9

    STM8AF52/62xx, STM8AF51/61xx 2 Description The STM8AF52xx, STM8AF62xx, STM8AF51xx, and STM8AF61xx automotive 8-bit microcontrollers described in this datasheet offer from 32 Kbytes to 128 Kbytes of non volatile memory and integrated true data EEPROM. They are referred to as high density ...

  • Page 10

    ... Product line-up 3 Product line-up .. Table 2. STM8AF52xx product line-up with CAN Order code Package STM8AF52AA LQFP80 (14x14) STM8AF528A STM8AF52A9 LQFP64 STM8AF5289 (10x10) STM8AF5269 STM8AF52A8 LQFP48 STM8AF5288 (7x7) STM8AF5268 Table 3. STM8AF62xx product line-up without CAN Order code Package STM8AF62AA LQFP80 (14x14) STM8AF628A STM8AF62A9 ...

  • Page 11

    STM8AF52/62xx, STM8AF51/61xx . Table 4. STM8AF/H/P51xx product line-up with CAN Order code Package STM8AF/H/P51AA LQFP80 STM8AF/H/P519A (14x14) STM8AF/H/P518A STM8AF/H/P51A9 STM8AF/H/P5199 LQFP64 STM8AF/H/P5189 (10x10) STM8AF/H/P5179 STM8AF/H/P5169 STM8AF/H/P51A8 STM8AF/H/P5198 LQFP48 STM8AF/H/P5188 (7x7) STM8AF/H/P5178 STM8AF/H/P5168 High density Data Flash RAM EEPROM program (bytes) ...

  • Page 12

    Product line-up ² Table 5. STM8AF/H/P61xx product line-up without CAN Order code Package STM8AF/H/P61AA LQFP80 STM8AF/H/P619A (14x14) STM8AF/H/P618A STM8AF/H/P61A9 STM8AF/H/P6199 LQFP64 STM8AF/H/P6189 (10x10) STM8AF/H/P6179 STM8AF/H/P6169 STM8AF/H/P61A8 STM8AF/H/P6198 LQFP48 (7x7) STM8AF/H/P6188 STM8AF/H/P6178 STM8AF/H/P6186 LQFP32 (7x7) STM8AF/H/P6176 12/106 High density Data Flash ...

  • Page 13

    STM8AF52/62xx, STM8AF51/61xx 4 Block diagram Figure 1. STM8A block diagram Reset Single wire debug interf. Master/slave automatic resynchronization 400 Kbit/s 10 Mbit/s LIN master SPI emul. 1 Mbit channels Reset block Clock controller Reset Detector POR PDR ...

  • Page 14

    Product overview 5 Product overview This section is intended to describe the family features that are actually implemented in the products covered by this datasheet. For more detailed information on each feature please refer to the STM8S and STM8A microcontroller ...

  • Page 15

    STM8AF52/62xx, STM8AF51/61xx 5.2 Single wire interface module (SWIM) and debug module (DM) 5.2.1 SWIM The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. The interface can be activated ...

  • Page 16

    Product overview 5.4.2 Write protection (WP) Write protection in application mode is intended to avoid unintentional overwriting of the memory. The write protection can be removed temporarily by executing a specific sequence in the user software. 5.4.3 Protection of user ...

  • Page 17

    STM8AF52/62xx, STM8AF51/61xx byte area. This keyword must be entered via the SWIM interface to temporarily unlock the device. If desired, the temporary unlock mechanism can be permanently disabled by the user through OPT6/NOPT6 option bytes. 5.5 Clock controller The clock ...

  • Page 18

    Product overview 5.5.3 128 kHz low-speed internal RC oscillator (LSI) The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the independent watchdog or the AWU wakeup timer. In systems which do ...

  • Page 19

    STM8AF52/62xx, STM8AF51/61xx 5.6 Low-power operating modes For efficient power management, the application can be put in one of four different low- power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time ...

  • Page 20

    Product overview option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. 5.7.2 Auto-wakeup counter This counter is used to cyclically ...

  • Page 21

    STM8AF52/62xx, STM8AF51/61xx TIM2, TIM3 - 16-bit general purpose timers ● 16-bit auto-reload up-counter ● 15-bit prescaler adjustable to fixed power of two ratios 1…32768 ● Timers with three or two individually configurable CAPCOM channels ● Interrupt sources ...

  • Page 22

    Product overview 5.8 Analog to digital converter (ADC) The STM8A products described in this datasheet contain a 10-bit successive approximation ADC with multiplexed input channels, depending on the package. The ADC name differs between the datasheet and ...

  • Page 23

    STM8AF52/62xx, STM8AF51/61xx ● High-precision baud rate generator system – Common programmable transmit and receive baud rates ● Programmable data word length ( bits) ● Configurable stop bits: Support for stop bits ● ...

  • Page 24

    Product overview communication interface which supports extensive LIN functions tailored for LIN slave applications. In LIN mode it is compliant to the LIN standards rev 1.2 to rev 2.1. Detailed feature list: LIN mode Master mode ● LIN break and ...

  • Page 25

    STM8AF52/62xx, STM8AF51/61xx 5.9.3 Serial peripheral interface (SPI) The devices covered by this datasheet contain one SPI. The SPI is available on all the supported packages. ● Maximum speed: 8 Mbit ● Full duplex synchronous transfers ● Simplex synchronous ...

  • Page 26

    Product overview ● Interrupt: – Successful address/data communication – Error condition – Wakeup from Halt ● Wakeup from Halt on address detection in slave mode 5.9.5 Controller area network interface (beCAN) The beCAN controller (basic enhanced CAN), interfaces the CAN ...

  • Page 27

    STM8AF52/62xx, STM8AF51/61xx The analog inputs are equipped with a low leakage analog switch. Additionally, the schmitt- trigger input stage on the analog I/Os can be disabled in order to reduce the device standby consumption. STM8A I/Os are designed to withstand ...

  • Page 28

    Pinouts and pin description 6 Pinouts and pin description 6.1 Package pinouts Figure 3. LQFP 80-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 V SSIO_1 VCAP V DDIO_1 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 (HS) PH0 HS) PH1 ( PH2 PH3 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 ...

  • Page 29

    STM8AF52/62xx, STM8AF51/61xx Figure 4. LQFP 64-pin pinout OSCIN/PA1 OSCOUT/PA2 TIM2_CH3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines stands for high sink capability ...

  • Page 30

    Pinouts and pin description Figure 5. LQFP 48-pin pinout 1. The CAN interface is only available on the STM8AF/H/P51xx and STM8AF52xx product lines stands for high sink capability. 30/106 ...

  • Page 31

    STM8AF52/62xx, STM8AF51/61xx Figure 6. LQFP 32-pin pinout 1. HS stands for high sink capability. Table 11. Legend/abbreviation for the pin description table Type Level Output speed Port and control configuration Reset state ...

  • Page 32

    Pinouts and pin description Table 12. STM8A microcontroller family pin description Pin number Pin name NRST ( PA1/OSCIN PA2/OSCOUT SSIO_1 ...

  • Page 33

    STM8AF52/62xx, STM8AF51/61xx Table 12. STM8A microcontroller family pin description (continued) Pin number Pin name DDA SSA REF PF0/AIN10 ...

  • Page 34

    Pinouts and pin description Table 12. STM8A microcontroller family pin description (continued) Pin number Pin name PE5/SPI_NSS PC0/ADC_ETR I PC1/TIM1_CH1 I PC2/TIM1_CH2 I/O 45 ...

  • Page 35

    STM8AF52/62xx, STM8AF51/61xx Table 12. STM8A microcontroller family pin description (continued) Pin number Pin name PE4 PE3/TIM1_BKIN I PE2/I C_SDA PE1/I C_SCL 70 ...

  • Page 36

    Pinouts and pin description 6.2 Alternate function remapping As shown in the rightmost column of different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 9: Option bytes on page default alternate function ...

  • Page 37

    STM8AF52/62xx, STM8AF51/61xx 7 Memory and register map 7.1 Memory map Figure 7. Register and memory map Table 13. Memory model 128K Flash program memory size 128K 96K 64K 48K 32K 1. if the device is containing the super set silicon ...

  • Page 38

    Memory and register map 7.2 Register map In this section the memory and register map of the devices covered by this datasheet is described. For a detailed description of the functionality of the registers, refer to the reference manual RM0016. ...

  • Page 39

    STM8AF52/62xx, STM8AF51/61xx Table 14. I/O port hardware register map (continued) Address Block 0x00 501E 0x00 501F 0x00 5020 Port G 0x00 5021 0x00 5022 0x00 5023 0x00 5024 0x00 5025 Port H 0x00 5026 0x00 5027 0x00 5028 0x00 5029 ...

  • Page 40

    Memory and register map Table 15. General hardware register map (continued) Address 0x00 50A0 0x00 50A1 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 ...

  • Page 41

    STM8AF52/62xx, STM8AF51/61xx Table 15. General hardware register map (continued) Address 0x00 50F3 0x00 50F4 to 0x00 50FF 0x00 5200 0x00 5201 0x00 5202 0x00 5203 0x00 5204 0x00 5205 0x00 5206 0x00 5207 0x00 5208 to 0x00 520F 0x00 5210 ...

  • Page 42

    Memory and register map Table 15. General hardware register map (continued) Address 0x00 5230 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 USART 0x00 5236 0x00 5237 0x00 5238 0x00 5239 0x00 523A 0x00 523B to 0x00 523F ...

  • Page 43

    STM8AF52/62xx, STM8AF51/61xx Table 15. General hardware register map (continued) Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E ...

  • Page 44

    Memory and register map Table 15. General hardware register map (continued) Address 0x00 5270 to 0x00 52FF 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 ...

  • Page 45

    STM8AF52/62xx, STM8AF51/61xx Table 15. General hardware register map (continued) Address 0x00 5320 0x00 5321 0x00 5322 0x00 5323 0x00 5324 0x00 5325 0x00 5326 0x00 5327 0x00 5328 0x00 5329 0x00 532A 0x00 532B 0x00 532C 0x00 532D 0x00 532E ...

  • Page 46

    Memory and register map Table 15. General hardware register map (continued) Address 0x00 5400 0x00 5401 0x00 5402 0x00 5403 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 to 0x00 541F 46/106 Block Register label ADC _CSR ADC_CR1 ...

  • Page 47

    STM8AF52/62xx, STM8AF51/61xx Table 15. General hardware register map (continued) Address 0x00 5420 0x00 5421 0x00 5422 0x00 5423 0x00 5424 0x00 5425 0x00 5426 0x00 5427 0x00 5428 0x00 5429 0x00 542A 0x00 542B beCAN 0x00 542C 0x00 542D 0x00 ...

  • Page 48

    Memory and register map Table 16. CPU/SWIM/debug module/interrupt controller registers Address Block Register label 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 (1) 0x00 7F05 CPU 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B ...

  • Page 49

    STM8AF52/62xx, STM8AF51/61xx Table 16. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label 0x00 7F90 DM_BK1RE 0x00 7F91 DM_BK1RH 0x00 7F92 DM_BK1RL 0x00 7F93 DM_BK2RE 0x00 7F94 DM_BK2RH 0x00 7F95 DM DM_BK2RL 0x00 7F96 DM_CR1 0x00 7F97 DM_CR2 0x00 7F98 ...

  • Page 50

    Interrupt table 8 Interrupt table Table 18. STM8A interrupt table Priority Source block — Reset Reset — TRAP SW interrupt 0 TLI External top level interrupt 1 AWU Auto-wakeup from Halt Clock 2 Main clock controller controller 3 MISC External ...

  • Page 51

    STM8AF52/62xx, STM8AF51/61xx 9 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, ...

  • Page 52

    Option bytes Table 19. Option bytes Option Option Addr. byte name no. Read-out 0x00 protection OPT0 4800 (ROP) 0x00 OPT1 User boot 4801 code 0x00 (UBC) NOPT1 4802 0x00 Alternate OPT2 AFR7 4803 function remapping 0x00 NOPT2 NAFR7 NAFR6 NAFR5 ...

  • Page 53

    STM8AF52/62xx, STM8AF51/61xx Table 19. Option bytes (continued) Option Option Addr. byte name no. 0x00 OPT8 4810 0x00 OPT9 4811 0x00 OPT10 4812 0x00 OPT11 4813 0x00 TMU OPT12 4814 0x00 OPT13 4815 0x00 OPT14 4816 0x00 OPT15 4817 0x00 OPT16 ...

  • Page 54

    Option bytes Table 20. Option byte description Option byte no. OPT0 OPT1 OPT2 54/106 Description ROP[7:0]: Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the STM8A microcontroller family reference manual (RM0016) section ...

  • Page 55

    STM8AF52/62xx, STM8AF51/61xx Table 20. Option byte description (continued) Option byte no. OPT3 OPT4 OPT5 OPT6 OPT7 OPT8 OPT9 OPT10 OPT11 Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock ...

  • Page 56

    Option bytes Table 20. Option byte description (continued) Option byte no. OPT12 OPT13 OPT14 OPT15 OPT16 OPT17 56/106 Description TMU_KEY 5 [7:0]: Temporary unprotection key 4 Temporary unprotection key: Must be different from 0x00 or 0xFF TMU_KEY 6 [7:0]: Temporary ...

  • Page 57

    STM8AF52/62xx, STM8AF51/61xx 10 Electrical characteristics 10.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

  • Page 58

    Electrical characteristics 10.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Pin input voltage 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage ...

  • Page 59

    STM8AF52/62xx, STM8AF51/61xx Table 22. Current characteristics Symbol I Total current into V VDDIO I Total current out of V VSSIO Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

  • Page 60

    Electrical characteristics 10.3 Operating conditions Table 25. General operating conditions Symbol f Internal CPU clock frequency CPU V V Standard operating voltage DD/ DDIO C EXT capacitor V CAP ESR of external capacitor ESL of external capacitor T Ambient temperature ...

  • Page 61

    STM8AF52/62xx, STM8AF51/61xx Table 26. Operating conditions at power-up/power-down Symbol VDD V DD Reset release delay t TEMP Reset generation delay Power-on reset V IT+ threshold Brown-out reset V IT- threshold Brown-out reset V HYS(BOR) hysteresis 1. Guaranteed ...

  • Page 62

    Electrical characteristics Table 27. Total current consumption in Run, Wait and Slow mode. General conditions for V apply Symbol Parameter Supply current in (1) I DD(RUN) Run mode Supply current in (1) I DD(RUN) Run mode Supply current ...

  • Page 63

    STM8AF52/62xx, STM8AF51/61xx Table 28. Total current consumption in Halt and Active-halt modes. General conditions for V = −40 ° °C unless otherwise stated applied Symbol Parameter Supply current in I DD(H) Halt mode Supply current in ...

  • Page 64

    Electrical characteristics Table 30. Programming current consumption Symbol Parameter I Programming current DD(PROG) Table 31. Typical peripheral current consumption V Symbol Parameter I TIM1 supply current DD(TIM1) I TIM2 supply current DD(TIM2) I TIM3 supply current DD(TIM3) I TIM4 supply ...

  • Page 65

    STM8AF52/62xx, STM8AF51/61xx Current consumption curves Figure 12 to Figure 17 RAM. Figure 12. Typ. I DD(RUN)HSE @ MHz, peripherals = on CPU 2.5 3 3.5 4 4.5 ...

  • Page 66

    Electrical characteristics 10.3.3 External clock sources and timing characteristics HSE external clock An HSE clock can be generated by feeding an external clock signal MHz to the OSCIN pin. Clock characteristics are subject to general operating ...

  • Page 67

    STM8AF52/62xx, STM8AF51/61xx Table 33. HSE oscillator characteristics Symbol Parameter R Feedback resistor F ( Recommended load capacitance Oscillator trans conductance m (2) t Startup time SU(HSE) 1. The oscillator needs two load capacitors ...

  • Page 68

    Electrical characteristics 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for V High-speed internal RC oscillator (HSI) Table 34. HSI oscillator characteristics Symbol f Frequency HSI HSI oscillator user trimming accuracy ACC HS HSI oscillator accuracy ...

  • Page 69

    STM8AF52/62xx, STM8AF51/61xx Low-speed internal RC oscillator (LSI) Subject to general operating conditions for V Table 35. LSI oscillator characteristics Symbol f Frequency LSI t LSI oscillator wakeup time su(LSI) 1. Data based on characterization results, not tested in production. Figure ...

  • Page 70

    Electrical characteristics 10.3.5 Memory characteristics Flash program memory/data EEPROM memory General conditions: T Table 36. Flash program memory/data EEPROM memory Symbol Operating voltage V DD (all modes, execution/write/erase) V Operating voltage (code execution) DD Standard programming time (including erase) for ...

  • Page 71

    STM8AF52/62xx, STM8AF51/61xx Table 38. Data memory Symbol T Temperature for writing and erasing WE Data memory endurance N WE (erase/write cycles) t Data retention time RET 1. The physical granularity of the memory is four bytes, so cycling is performed ...

  • Page 72

    Electrical characteristics 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for V unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down ...

  • Page 73

    STM8AF52/62xx, STM8AF51/61xx Figure 22. Typical V Figure 23. Typical pull-up resistance R and four temperatures 2 ...

  • Page 74

    Electrical characteristics Figure 24. Typical pull-up current I 1. The pull- pure resistor (slope goes through 0). Typical output level curves Figure 25 to Figure 34 show typical output level curves measured with output on a single pin. ...

  • Page 75

    STM8AF52/62xx, STM8AF51/61xx Figure 29. Typ ports) -40°C 1.5 25°C 85°C 1.25 125°C 1 0.75 0.5 0. [mA] OL Figure 31. Typ (standard ...

  • Page 76

    Electrical characteristics 10.3.7 Reset pin characteristics Subject to general operating conditions for V Table 40. NRST pin characteristics Symbol V NRST low-level input voltage IL(NRST) V NRST high-level input voltage IH(NRST) V NRST low-level output voltage OL(NRST) R NRST pull-up ...

  • Page 77

    STM8AF52/62xx, STM8AF51/61xx Figure 36. Typical NRST pull-up resistance Figure 37. Typical NRST pull-up current I 140 120 100 The reset network shown in must ensure that the level on the NRST pin ...

  • Page 78

    Electrical characteristics Figure 38. Recommended reset pin protection External reset circuit (optional) 10.3.8 TIM and 4 electrical specifications Subject to general operating conditions for V Table 41. TIM and 4 electrical specifications Symbol f ...

  • Page 79

    STM8AF52/62xx, STM8AF51/61xx SPI interface 10.3.9 Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions. t MASTER Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. ...

  • Page 80

    Electrical characteristics Figure 39. SPI timing diagram in slave mode and with CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT ...

  • Page 81

    STM8AF52/62xx, STM8AF51/61xx Figure 41. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are at CMOS levels: 0 ...

  • Page 82

    Electrical characteristics 2 10.3. interface characteristics 2 Table 43 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t SDA ...

  • Page 83

    STM8AF52/62xx, STM8AF51/61xx 10.3.11 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 44. ADC characteristics Symbol f ADC clock frequency ADC V Analog supply DDA V Positive reference voltage REF+ V Negative reference voltage REF- V Conversion ...

  • Page 84

    Electrical characteristics Table 45. ADC accuracy for V Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Total ...

  • Page 85

    STM8AF52/62xx, STM8AF51/61xx 10.3.12 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until ...

  • Page 86

    Electrical characteristics Electromagnetic interference (EMI) Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin loading. Table 47. EMI data Symbol Parameter Peak level S EMI SAE EMI level 1. Data based on characterization ...

  • Page 87

    ... Symbol LU Static latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). Parameter ...

  • Page 88

    Electrical characteristics 10.4 Thermal characteristics In case the maximum chip junction temperature (T operating conditions degrees Celsius, may be calculated using the following equation: Jmax Equation 3 where: is the maximum ambient temperature in °C T Amax ...

  • Page 89

    STM8AF52/62xx, STM8AF51/61xx 10.4.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 48: Ordering information scheme on page The following example shows how to calculate the temperature range needed ...

  • Page 90

    Package characteristics 11 Package characteristics ® 11.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are ...

  • Page 91

    STM8AF52/62xx, STM8AF51/61xx 11.2 Package mechanical data Figure 44. 80-pin low profile quad flat package ( Pin 1 identification 1 Table 51. 80-pin low profile quad flat package mechanical data Dim ...

  • Page 92

    Package characteristics Figure 45. 64-pin low profile quad flat package (10 x 10) Pin 1 identification Table 52. 64-pin low profile quad flat package mechanical data Dim θ ...

  • Page 93

    STM8AF52/62xx, STM8AF51/61xx Figure 46. 48-pin low profile quad flat package ( Table 53. 48-pin low profile quad flat package mechanical data Dim θ Values in ...

  • Page 94

    Package characteristics Figure 47. 32-pin low profile quad flat package ( Table 54. 32-pin low profile quad flat package mechanical data Dim θ Values in ...

  • Page 95

    STM8AF52/62xx, STM8AF51/61xx 12 Ordering information Figure 48. Ordering information scheme Example: Product class 8-bit automotive microcontroller Program memory type F = Flash + EEPROM P = FASTROM H = Flash no EEPROM Device family 52 = Silicon rev U, CAN/LIN ...

  • Page 96

    ... In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. ...

  • Page 97

    ... STM8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes: ST visual develop Full-featured integrated development environment from STMicroelectronics, featuring: ● Seamless integration of C and ASM toolsets ● Full-featured debugger ● ...

  • Page 98

    STM8 development tools 13.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST ...

  • Page 99

    STM8AF52/62xx, STM8AF51/61xx 14 Revision history Table 55. Document revision history Date 31-Jan-2008 22-Aug-2008 Revision Rev 1 Initial release Added ‘H’ products to the datasheet (Flash no EEPROM). Features on page 1: Updated Memories, management, Communication interfaces by 1. Table 1: ...

  • Page 100

    Revision history Table 55. Document revision history (continued) Date 22-Aug-2008 16-Sep-2008 100/106 Revision Table 34: Removed ACC parameters; amended data and footnotes. Amended data of ‘RAM and hardware Table 36: Updated names and data of N Table 39: Added V ...

  • Page 101

    STM8AF52/62xx, STM8AF51/61xx Table 55. Document revision history (continued) Date 01-Jul-2009 Revision Added ‘STM8AH61xx’ and ‘STM8AH51xx to document header. Updated Features on page 1 temperature, ADC and I/Os). Updated Table 1: Device summary Updated Kbytes value of program memory in Chapter ...

  • Page 102

    Revision history Table 55. Document revision history (continued) Date 01-Jul-2009 22-Oct-2009 102/106 Revision Removed Table 22: Total current consumption and timing in halt, fast active halt and slow active halt modes at V Added Table 29: Oscillator current consumption Added ...

  • Page 103

    STM8AF52/62xx, STM8AF51/61xx Table 55. Document revision history (continued) Date 13-Apr-2010 08-Jul-2010 Revision Updated title on cover page. Modified cover page header to clarify the part numbers covered by the datasheets. Updated add ‘P’ order codes. Changed definition of ‘P’ order ...

  • Page 104

    Revision history Table 55. Document revision history (continued) Date 3&-Jan-2011 104/106 Revision Modified references to reference manual, and Flash programming manual in the whole document. Added reference to AEC Q100 standard on cover page. Renamed timer types as follows: – ...

  • Page 105

    STM8AF52/62xx, STM8AF51/61xx Table 55. Document revision history (continued) Date 3&-Jan-2011 Revision Renamed Fast Active Halt mode to Active-halt mode with regulator on, and Slow Active Halt mode to Active-halt mode with regulator off, updated Section 5.6: Low-power operating Total current ...

  • Page 106

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...