STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
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Revision history
Table 55.
Document revision history (continued)
Date
3&-Jan-2011
104/106
Revision
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of high density Flash program memory.
Updated number of I/Os for devices in 80-, 64-, and 48-pin packages
in
Table 2: STM8AF52xx product line-up with
STM8AF62xx product line-up without
STM8AF/H/P51xx product line-up with
STM8AF/H/P61xx product line-up without
Added TMU brief description in
EEPROM, updated TMU_MAXATT description in
byte
description, and TMU_MAWATT reset value in
bytes.
Updated clock sources in clock controller features
Added
Table 6: Peripheral clock gating bits
Rev 8
Added calibration using TIM3 in
Added
Table 9: ADC naming
peripheral naming
correspondence.
Updated SPI data rate to f
peripheral interface
(SPI).
Added reset state in
description
table.
Table 12: STM8A microcontroller family pin
Note
2, added
Note 3
PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to
TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register
Removed I2C_PECR register.
Added
Note 1
for Px_IDR registers in
register
map. Updated register reset values for Px_IDR and PD_CR1
registers.
Replaced tables describing register maps and reset values for non-
volatile memory, global configuration, reset status, TMU, clock
controller, interrupt controller, timers, communication interfaces, and
ADC, by
Table 15: General hardware register
module register map.
Doc ID 14395 Rev 8
STM8AF52/62xx, STM8AF51/61xx
Changes
CAN,
Table 3:
CAN,
Table 4:
CAN, and
Table 5:
CAN.
Section 5.4: Flash program and data
Table 20: Option
Table 19: Option
(Section
in
Section
5.5.6.
Section 5.7.2: Auto-wakeup
and
Table 10: Communication
/2 in
Section 5.9.3: Serial
MASTER
Table 11: Legend/abbreviation for the pin
description: modified
related to PD1/SWIM, corrected wpu input for
map: Removed CAN register CLK_CANCCR.
Table 14: I/O port hardware
map. Added debug
5.5.1).
counter.