STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
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STM8AF52/62xx, STM8AF51/61xx
5.2
Single wire interface module (SWIM) and debug module (DM)
5.2.1
SWIM
The single wire interface module, SWIM, together with an integrated debug module, permits
non-intrusive, real-time in-circuit debugging and fast memory programming. The interface
can be activated in all device operation modes and can be connected to a running device
(hot plugging).The maximum data transmission speed is 145 bytes/ms.
5.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-flavored
emulator. Besides memory and peripheral operation, CPU operation can also be monitored
in real-time by means of shadow registers.
R/W of RAM and peripheral registers in real-time
R/W for all resources when the application is stopped
Breakpoints on all program-memory instructions (software breakpoints), except the
interrupt vector table
Two advanced breakpoints and 23 predefined breakpoint configurations
5.3
Interrupt controller
Nested interrupts with three software priority levels
24 interrupt vectors with hardware priority
Five vectors for external interrupts (up to 37 depending on the package)
Trap and reset interrupts
5.4
Flash program and data EEPROM
32 Kbytes to 128 Kbytes of high density single voltage Flash program memory
Up to 2 Kbytes true (not emulated) data EEPROM
Read while write: writing in the data memory is possible while executing code in the
Flash program memory
Temporary memory unprotection (TMU)
section Readout protection of RM0016
contact your local ST Sales Office.The device setup is stored in a user option area in
the non volatile memory
5.4.1
Architecture
The memory is organized in blocks of 128 bytes each
Read granularity: 1 word = 4 bytes
Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
Writing, erasing, word and block management is handled automatically by the memory
interface.
Doc ID 14395 Rev 8
Product overview
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