STM8AF52AA STMicroelectronics, STM8AF52AA Datasheet - Page 19

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STM8AF52AA

Manufacturer Part Number
STM8AF52AA
Description
STM8AF52 CAN Line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8AF52AA

Max Fcpu
24 MHz
Program Memory
32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memory
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
2 Kbytes to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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STM8AF52/62xx, STM8AF51/61xx
5.6
5.7
5.7.1
Low-power operating modes
For efficient power management, the application can be put in one of four different low-
power modes. You can configure each mode to obtain the best compromise between lowest
power consumption, fastest start-up time and available wakeup sources.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.
Timers
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
option bytes. Once the watchdog is activated, it cannot be disabled by the user program
without going through reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
timing perfectly. The application software must refresh the counter before time-out and
during a limited time window. If the counter is refreshed outside this time window, a reset is
issued.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve malfunctions due to hardware
or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure. If the hardware watchdog feature is enabled through the device
Wait mode
In this mode, the CPU is stopped but peripherals are kept running. The wakeup is
performed by an internal or external interrupt or reset.
Active-halt mode with regulator on
In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is
generated at programmable intervals by the auto wake up unit (AWU). The main
voltage regulator is kept powered on, so current consumption is higher than in Active-
halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the
internal AWU interrupt, external interrupt or reset.
Active-halt mode with regulator off
This mode is the same as Active-halt with regulator on, except that the main voltage
regulator is powered off, so the wake up time is slower.
Halt mode
CPU and peripheral clocks are stopped, the main voltage regulator is powered off.
Wakeup is triggered by external event or reset.
Doc ID 14395 Rev 8
Product overview
19/106

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