STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
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STM8AF52/62xx, STM8AF51/61xx
Table 12.
STM8A microcontroller family pin description (continued)
Pin number
Pin name
66 52
-
-
PE4
67 53 37
-
PE3/TIM1_BKIN I/O
2
68 54 38
-
PE2/I
C_SDA
2
69 55 39
-
PE1/I
C_SCL
70 56 40
-
PE0/CLK_CCO I/O
71
-
-
-
PI6
72
-
-
-
PI7
73 57 41 25 PD0/TIM3_CH2 I/O
(3)
74 58 42 26
PD1/SWIM
75 59 43 27 PD2/TIM3_CH1 I/O
76 60 44 28 PD3/TIM2_CH2 I/O
PD4/TIM2_CH1/
77 61 45 29
BEEP
PD5/
78 62 46 30
LINUART_TX
PD6/
79 63 47 31
LINUART_RX
(4)
80 64 48 32
PD7/TLI
1. In Halt/Active-halt mode, this pin behaves as follows:
- The input/output path is disabled.
- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.
- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the
corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in
Halt/Active-halt mode.
2. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to V
not implemented)
3. The PD1 pin is in input pull-up during the reset phase and after reset release.
4. If this pin is configured as interrupt pin, it will trigger the TLI.
Input
Output
I/O
X
X
X
— O1
X
X
X
X
— O1
X
(2)
I/O
X
X
— O1 T
(2)
I/O
X
X
— O1 T
X
X
X
— O3
X
I/O
X
X
— O1
X
I/O
X
X
— O1
X
X
X
X
HS O3
X
I/O
X
X
X
HS O4
X
X
X
X
HS O3
X
X
X
X
HS O3
X
I/O
X
X
X
HS O3
X
I/O
X
X
X
— O1
X
X
I/O
X
X
— O1
X
X
I/O
X
X
X
— O1
X
Doc ID 14395 Rev 8
Pinouts and pin description
Main
Alternate
Default
function
function
alternate
(after
after remap
function
reset)
[option bit]
X
Port E4
Timer 1 -
X
Port E3
break input
2
-
Port E2
I
C data
2
-
Port E1
I
C clock
Configurable
X
Port E0
clock output
X
Port I6
X
Port I7
TIM1_BKIN
Timer 3 -
[AFR3]/
X
Port D0
channel 2
CLK_CCO
[AFR2]
SWIM data
X
Port D1
interface
Timer 3 -
TIM2_CH3
X
Port D2
channel 1
[AFR1]
Timer 2 -
ADC_ETR
X
Port D3
channel 2
[AFR0]
Timer 2 -
BEEP output
X
Port D4
channel 1
[AFR7]
LINUART
X
Port D5
data transmit
LINUART
Port D6
data receive
X
Top level
X
Port D7
interrupt
DD
are
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