STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Page 38/106

Download datasheet (2Mb)Embed
PrevNext
Memory and register map
7.2
Register map
In this section the memory and register map of the devices covered by this datasheet is
described. For a detailed description of the functionality of the registers, refer to the
reference manual RM0016.
Table 14.
I/O port hardware register map
Address
Block
0x00 5000
0x00 5001
0x00 5002
Port A
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
Port B
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
Port C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
Port D
0x00 5012
0x00 5013
0x00 5014
0x00 5015
0x00 5016
Port E
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
Port F
0x00 501C
0x00 501D
38/106
STM8AF52/62xx, STM8AF51/61xx
Register label
Register name
PA_ODR
Port A data output latch register
PA_IDR
Port A input pin value register
PA_DDR
Port A data direction register
PA_CR1
Port A control register 1
PA_CR2
Port A control register 2
PB_ODR
Port B data output latch register
PB_IDR
Port B input pin value register
PB_DDR
Port B data direction register
PB_CR1
Port B control register 1
PB_CR2
Port B control register 2
PC_ODR
Port C data output latch register
PB_IDR
Port C input pin value register
PC_DDR
Port C data direction register
PC_CR1
Port C control register 1
PC_CR2
Port C control register 2
PD_ODR
Port D data output latch register
PD_IDR
Port D input pin value register
PD_DDR
Port D data direction register
PD_CR1
Port D control register 1
PD_CR2
Port D control register 2
PE_ODR
Port E data output latch register
PE_IDR
Port E input pin value register
PE_DDR
Port E data direction register
PE_CR1
Port E control register 1
PE_CR2
Port E control register 2
PF_ODR
Port F data output latch register
PF_IDR
Port F input pin value register
PF_DDR
Port F data direction register
PF_CR1
Port F control register 1
PF_CR2
Port F control register 2
Doc ID 14395 Rev 8
Reset
status
0x00
(1)
0xXX
0x00
0x00
0x00
0x00
(1)
0xXX
0x00
0x00
0x00
0x00
(1)
0xXX
0x00
0x00
0x00
0x00
(1)
0xXX
0x00
0x02
0x00
0x00
(1)
0xXX
0x00
0x00
0x00
0x00
(1)
0xXX
0x00
0x00
0x00