STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Page 43/106

Download datasheet (2Mb)Embed
PrevNext
STM8AF52/62xx, STM8AF51/61xx
Table 15.
General hardware register map (continued)
Address
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
Block
Register label
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1_CCMR1
TIM1 capture/compare mode register 1
TIM1_CCMR2
TIM1 capture/compare mode register 2
TIM1_CCMR3
TIM1 capture/compare mode register 3
TIM1_CCMR4
TIM1 capture/compare mode register 4
TIM1 capture/compare enable register
TIM1_CCER1
TIM1 capture/compare enable register
TIM1_CCER2
TIM1_CNTRH
TIM1
TIM1_CNTRL
TIM1_PSCRH
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1_CCR1H
TIM1 capture/compare register 1 high
TIM1_CCR1L
TIM1 capture/compare register 1 low
TIM1_CCR2H
TIM1 capture/compare register 2 high
TIM1_CCR2L
TIM1 capture/compare register 2 low
TIM1_CCR3H
TIM1 capture/compare register 3 high
TIM1_CCR3L
TIM1 capture/compare register 3 low
TIM1_CCR4H
TIM1 capture/compare register 4 high
TIM1_CCR4L
TIM1 capture/compare register 4 low
TIM1_BKR
TIM1_DTR
TIM1_OISR
Doc ID 14395 Rev 8
Memory and register map
Register name
TIM1 control register 1
TIM1 control register 2
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1 status register 2
TIM1 event generation register
1
2
TIM1 counter high
TIM1 counter low
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 break register
TIM1 dead-time register
TIM1 output idle state register
Reset
status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
43/106