STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
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Page 79/106

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STM8AF52/62xx, STM8AF51/61xx
SPI interface
10.3.9
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
conditions. t
MASTER
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 42.
SPI characteristics
Symbol
Parameter
f
SCK
SPI clock frequency
1/t
c(SCK)
t
r(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
t
f(SCK)
(3)
t
NSS setup time
su(NSS)
(3)
t
NSS hold time
h(NSS)
(3)
t
w(SCKH)
SCK high and low time
(3)
t
w(SCKL)
(3)
t
su(MI)
Data input setup time
(3)
t
su(SI)
(3)
t
h(MI)
Data input hold time
(3)
t
h(SI)
(3)(4)
t
Data output access time
a(SO)
(3)(5)
t
Data output disable time
dis(SO)
(3)
t
Data output valid time
v(SO)
(3)
t
Data output valid time
v(MO)
(3)
t
h(SO)
Data output hold time
(3)
t
h(MO)
1. f
< f
/2.
SCK
MASTER
2. The pad has to be configured accordingly (fast mode).
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
frequency, and V
MASTER
= 1/f
.
MASTER
Conditions
Master mode
V
< 4.5 V
DD
Slave mode
V
= 4.5 V to 5.5 V
DD
Slave mode
Slave mode
Master mode,
f
= 8 MHz, f
= 4 MHz
MASTER
SCK
Master mode
Slave mode
Master mode
Slave mode
Slave mode
Slave mode
V
< 4.5 V
Slave mode
DD
(after enable edge)
V
= 4.5 V to 5.5 V
DD
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Doc ID 14395 Rev 8
Electrical characteristics
Table 42
are derived from tests
supply voltage
DD
Min
Max
0
10
(1)
0
6
(1)
0
8
(2)
25
4 * t
MASTER
70
110
140
5
5
7
10
3* t
MASTER
25
75
53
30
31
12
Unit
MHz
ns
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