STM8AF52AA

Manufacturer Part NumberSTM8AF52AA
DescriptionSTM8AF52 CAN Line
ManufacturerSTMicroelectronics
STM8AF52AA datasheet
 


Specifications of STM8AF52AA

Max Fcpu24 MHzProgram Memory32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memoryup to 2 Kbytes true data EEPROM; endurance 300 kcyclesRam2 Kbytes to 6 Kbytes
Advanced Control Timer16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Page 88/106

Download datasheet (2Mb)Embed
PrevNext
Electrical characteristics
10.4
Thermal characteristics
In case the maximum chip junction temperature (T
operating conditions
T
, in degrees Celsius, may be calculated using the following equation:
Jmax
Equation 3
where:
is the maximum ambient temperature in °C
T
Amax
Θ
is the package junction-to-ambient thermal resistance in ° C/W
JA
P
is the sum of P
Dmax
P
is the product of I
INTmax
internal power.
P
represents the maximum power dissipation on output pins
I/Omax
where:
Equation 4
taking into account the actual V
application.
Table 50.
Thermal characteristics
Symbol
Thermal resistance junction-ambient
Θ
JA
LQFP 80 - 14 x 14 mm
Thermal resistance junction-ambient
Θ
JA
LQFP 64 - 10 x 10 mm
Thermal resistance junction-ambient
Θ
JA
LQFP 48 - 7 x 7 mm
Thermal resistance junction-ambient
Θ
JA
LQFP 32 - 7 x 7 mm
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.4.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
88/106
Jmax
is exceeded, the functionality of the device cannot be guaranteed.
T
= T
+ (P
Jmax
Amax
Dmax
and P
(P
INTmax
I/Omax
Dmax
and V
, expressed in Watts. This is the maximum chip
DD
DD
= Σ (V
) + Σ((V
P
* I
I/Omax
OL
OL
/ I
and V
/ I
OL
OL
OH
OH
(1)
Parameter
Doc ID 14395 Rev 8
STM8AF52/62xx, STM8AF51/61xx
) specified in
Table 25: General
x Θ
)
JA
= P
+ P
)
INTmax
I/Omax
- V
) * I
)
DD
OH
OH
of the I/Os at low- and high-level in the
Value
38
46
57
59
Unit
°C/W
°C/W
°C/W
°C/W