STM8S207RB STMicroelectronics, STM8S207RB Datasheet - Page 14

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STM8S207RB

Manufacturer Part Number
STM8S207RB
Description
Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S207RB

Max Fcpu
up to 24 MHz, 0 wait states @ fCPU≤ 16 MHz
Program
up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
Data
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
up to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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Product overview
4.2
4.3
4.4
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Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
Interrupt controller
Flash program and data EEPROM memory
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 37 external interrupts on six vectors including TLI
Trap and reset interrupts
Up to 128 Kbytes of high density Flash program single voltage Flash memory
Up to 2K bytes true data EEPROM
Read while write: Writing in data memory possible while executing code in program
memory.
User option byte area
Doc ID 14733 Rev 12
Figure
2.
STM8S207xx, STM8S208xx

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