STM8AF5179 STMicroelectronics, STM8AF5179 Datasheet - Page 104

• Manufacturer Part Number: STM8AF5179
• Description: Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 V to 5.5 V
• Manufacturer: STMicroelectronics

Specifications of STM8AF5179

• Max Fcpu: 24 MHz
• Program Memory: 32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
• Data Memory: up to 2 Kbytes true data EEPROM; endurance 300 kcycles
• Ram: 2 Kbytes to 6 Kbytes
• Advanced Control Timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

Revision history
104/106
Table 55.
3&-Jan-2011
Date
Document revision history (continued)
Revision
Rev 8
Modified references to reference manual, and Flash programming
manual in the whole document.
Added reference to AEC Q100 standard on cover page.
Renamed timer types as follows:
– Auto-reload timer to general purpose timer
– Multipurpose timer to advanced control timer
– System timer to basic timer
Introduced concept of high density Flash program memory.
Updated number of I/Os for devices in 80-, 64-, and 48-pin packages
in
STM8AF62xx product line-up without
STM8AF/H/P51xx product line-up with
STM8AF/H/P61xx product line-up without
Added TMU brief description in
EEPROM, updated TMU_MAXATT description in
byte
bytes.
Updated clock sources in clock controller features
Added
Added calibration using TIM3 in
Added
peripheral naming
Updated SPI data rate to f
peripheral interface
Added reset state in
description
Table 12: STM8A microcontroller family pin
Note
PE1 and PE2, and renamed TIMn_CCx and TIMn_NCCx to
TIMn_CHx and TIMn_CHxN, respectively.
Section 7.2: Register
Removed I2C_PECR register.
Added
register
registers.
Replaced tables describing register maps and reset values for non-
volatile memory, global configuration, reset status, TMU, clock
controller, interrupt controller, timers, communication interfaces, and
ADC, by
module register map.
Doc ID 14395 Rev 8
Table 2: STM8AF52xx product line-up with
description, and TMU_MAWATT reset value in
2, added
Table 6: Peripheral clock gating bits
Table 9: ADC naming
Note 1
map. Updated register reset values for Px_IDR and PD_CR1
Table 15: General hardware register
table.
for Px_IDR registers in
Note 3
correspondence.
(SPI).
Table 11: Legend/abbreviation for the pin
related to PD1/SWIM, corrected wpu input for
map: Removed CAN register CLK_CANCCR.
MASTER
and
Changes
STM8AF52/62xx, STM8AF51/61xx
Section 5.4: Flash program and data
Section 5.7.2: Auto-wakeup
Table 10: Communication
/2 in
CAN,
Table 14: I/O port hardware
Section 5.9.3: Serial
CAN, and
CAN.
in
description: modified
Table 4:
CAN,
Section
map. Added debug
Table 5:
Table 20: Option
(Section
Table 3:
Table 19: Option
5.5.6.
5.5.1).
counter.