STM8AF5268 STMicroelectronics, STM8AF5268 Datasheet - Page 23

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STM8AF5268

Manufacturer Part Number
STM8AF5268
Description
STM8AF52 CAN Line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8AF5268

Max Fcpu
24 MHz
Program Memory
32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memory
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
2 Kbytes to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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STM8AF52/62xx, STM8AF51/61xx
5.9.2
Universal asynchronous receiver/transmitter with LIN support
(LINUART)
The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
High-precision baud rate generator system
Programmable data word length (8 or 9 bits)
Configurable stop bits: Support for 1 or 2 stop bits
LIN master mode:
Transmitter clock output for synchronous communication
Separate enable bits for transmitter and receiver
Transfer detection flags:
Parity control:
Four error detection flags:
Six interrupt sources with flags:
Two interrupt vectors:
Reduced power consumption mode
Wakeup from mute mode (by idle line detection or address mark detection)
Two receiver wakeup modes:
Common programmable transmit and receive baud rates up to f
LIN break and delimiter generation
LIN break and delimiter detection with separate flag and interrupt source for
readback checking.
Receive buffer full
Transmit buffer empty
End of transmission flags
Transmits parity bit
Checks parity of received data byte
Overrun error
Noise error
Frame error
Parity error
Transmit data register empty
Transmission complete
Receive data register full
Idle line received
Parity error
LIN break and delimiter detection
Transmitter interrupt
Receiver interrupt
Address bit (MSB)
Idle line
Doc ID 14395 Rev 8
Product overview
MASTER
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