STM32TS60 STMicroelectronics, STM32TS60 Datasheet

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... USART (ISO 7816 interface, LIN, IrDA – SPIs (18 Mbit/s and 9 Mbit/s) – USB 2.0 full-speed interface ■ CRC calculation unit, 96-bit unique ID ■ Packages are ECOPACK® Doc ID 16925 Rev 3 STM32TS60 FBGA UFBGA144 7 × Unsawn wafer IC/OC/PWM or pulse counter and quadrature (incremental) encoder input window) ...

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... Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . 12 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Universal synchronous/asynchronous receiver transmitter (USART Serial peripheral interface (SPI Universal serial bus (USB GPIOs (general-purpose inputs/outputs Analog-to-digital converter (ADC Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial wire JTAG debug port (SWJ-DP Doc ID 16925 Rev 3 STM32TS60 ...

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... STM32TS60 5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 16925 Rev 3 Contents 3/27 ...

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... List of tables List of tables Table 1. STM32TS60 device features and peripheral counts Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. STM32TS60 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. UFBGA144 - ultra low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5. Ordering information scheme for package devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6 ...

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... STM32TS60 List of figures Figure 1. STM32TS60 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. STM32TS60 device UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4. UFBGA144 - ultra low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 16925 Rev 3 List of figures 5/27 ...

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... PMatrix™ area detection) offering a highly integrated solution and improved performances compared to existing market solutions. The STM32TS60 supports a touch panel with a matrix columns and 64 rows. For further information on any aspect of this device or to get access to the corresponding datasheet, reference manual, die specification, and programming manual, please contact your nearest ST Sales Office ...

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... STM32TS60 2.1 Device overview Table 1. STM32TS60 device features and peripheral counts Peripheral Flash (Kbytes) SRAM (Kbytes) General-purpose timers Communication GPIOs 12-bit synchronized ADC (number of channels) CPU frequency Operating voltage Operating temperatures Packages SPI USART USB Ambient Junction Doc ID 16925 Rev 3 Description ...

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... Description Figure 1. STM32TS60 device block diagram JTRST JTDI JTCK/SWCLK JTMS/SWDAT JTDO NRESET PA0 as AF 138 GPIO MISO,MOSI,SCK NSS COL[1:81 ROW[1:64 8/27 SW/JTAG ARM® Ibus TM Cortex -M3 CPU Dbus MHz MAX SYSTIC System NVIC 8-channel DMA SUPPLY SUPERVISOR POR/PDR ...

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... The 10 Kbytes of embedded SRAM can be accessed (read/write) at CPU clock speed with 0 wait states. 2.2.5 Nested vectored interrupt controller (NVIC) The STM32TS60 embeds a nested vectored interrupt controller which can handle maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3) and 16 priority levels. Features include: ● ...

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... The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 10/27 is below a specified threshold threshold. An interrupt can be generated PVD threshold and/or when V PVD Doc ID 16925 Rev 3 STM32TS60 , without the need for an POR/PDR is higher than the V DD PVD ...

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... This regulator is always enabled after reset disabled in Standby mode, providing high impedance output. 2.2.11 Low power modes The STM32TS60 device supports three Low power modes to achieve the best compromise between Low power consumption, short startup time, and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped ...

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... The backup registers include ten 16-bit registers which are used to store 20 bytes of user application data. 2.2.16 Timers and watchdogs The STM32TS60 device includes two general-purpose timers, two watchdog timers and a SysTick timer. Table 2 compares the features of the advanced-control and general-purpose timers. ...

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... STM32TS60 These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from one to three hall-effect sensors. Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler clocked from an independent 40 kHz internal RC and operates independently of the main clock, it can operate in Stop and Standby modes ...

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... Description 2.2.20 Universal serial bus (USB) The STM32TS60 device embeds a USB device peripheral compatible with the USB full- speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has a software-configurable endpoint setting and suspend/resume support. The dedicated 48-MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) ...

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... STM32TS60 3 Ballout and pin description Figure 2. STM32TS60 device UFBGA144 ballout PI6 PI12 PI14 A B PI15 PI0 PI5 C PI13 PI17 PI8 D PI1 PI2 PI9 E PE0 PE4 PE6 F PE8 PE1 PE2 G PE11 PE12 PE10 H PE15 PE13 PE14 J PD3 PD4 PD2 K PD5 PD0 ...

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... Ballout and pin description Table 3. STM32TS60 pin definitions Pin Pin Pin (1)(2) (3) no. type level A1 I/O PI6/COL A2 I/O PI12/COL A3 I/O PI14/COL A4 I/O PI3/COL A5 I/O PG6/COL A6 S VDD_1 A7 S VSS_1 A8 I/O PA0/WAKE-UP/SPI1_NSS A9 I/O PF1/COL/ROW A10 I/O PF3/COL/ROW A11 I/O PF5/COL/ROW A12 I/O PF7/COL/ROW B1 I/O PI15/COL B2 I/O PI0/COL B3 I/O PI5/COL B4 I/O PI4/COL B5 I/O PG8/COL B6 I/O PA12/OSC_OUT/COL PA5/I2C2_SCL/USART2_CTS/SPI2_SCK(remap)/TIM B7 I/O FT ...

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... STM32TS60 Table 3. STM32TS60 pin definitions (continued) Pin Pin Pin (1)(2) (3) no. type level C1 I/O PI13/COL C2 I/O PI7/COL C3 I/O PI8/COL C4 I/O PI10/COL C5 I/O PC12/ROW C6 I/O PA11/OSC_IN/COL C7 I/O FT PA8 PA6/I2C2_SDA/SPI2_MISO(remap)/USART2_RTS/TI C8 I/O M3_CH2/TIM2_CH2(remap)/MCO C9 I/O PA1/USBDP/I2C2_SMBAI C10 I/O PF15/COL/ROW C11 I/O PF10/COL/ROW C12 I/O PF8/COL/ROW D1 I/O PI1/COL D2 I/O PI2/COL D3 I/O PI9/COL D4 I/O PI11/COL D5 I/O PB6/TIM2_CH1/TRACED0/COL D6 I/O PA7/SPI1_MOSI/USART2_RX D7 I/O FT PA3/SPI1_SCK/I2C1_SCL/USART2_CK D8 I/O FT PA4/SPI1_MISO/I2C1_SDA/USART2_TX ...

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... Ballout and pin description Table 3. STM32TS60 pin definitions (continued) Pin Pin Pin (1)(2) (3) no. type level D10 I/O PF6/COL/ROW D11 I/O PF0/COL/ROW D12 I/O PF4/COL/ROW E1 I/O PE0/ROW E2 I/O PE4/ROW E3 I/O PE6/ROW E4 I/O PE5/ROW E5 I/O PB9/TIM2_CH4/TRACED3/COL E6 I/O PC0/ROW E7 I/O PC1/ROW E8 I/O PG0/COL PA10/SPI2_MOSI(remap)/TIM3_CH3/TIM2_CH3 E9 I/O (remap)/COL E10 I/O PB1/SPI2_MISO/COL E11 I/O PF2/COL/ROW E12 I/O PF14/COL/ROW F1 I/O PE8/ROW F2 I/O PE1/ROW ...

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... STM32TS60 Table 3. STM32TS60 pin definitions (continued) Pin Pin Pin (1)(2) (3) no. type level F12 I/O PG12/COL G1 I/O PE11/ROW G2 I/O PE12/ROW G3 I/O PE10/ROW G4 I/O PE9/ROW G5 I/O PC3/ROW G6 I BOOT0 G7 I/O PA9/BOOT1/COL G8 I/O PB0/SPI2_SCK/COL G9 I/O PB2/SPI2_MOSI/COL G10 I/O PG14/COL G11 I/O PG4/COL G12 I/O PG15/COL H1 I/O PE15/ROW H2 I/O PE13/ROW H3 I/O PE14/ROW H4 I/O PE7/ROW H5 I/O PC4/ROW H6 I/O PA14/JTCK/SWCLK/COL H7 I/O PA13/JTMS/SWDIO/COL H8 I/O PG2/COL H9 I/O PG3/COL H10 I/O PG7/COL ...

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... Ballout and pin description Table 3. STM32TS60 pin definitions (continued) Pin Pin Pin (1)(2) (3) no. type level J6 I/O PC10/ROW J7 I/O PB4/COL/JTRST J8 I/O PG1/COL J9 I/O PH13/COL J10 I/O PH7/COL J11 I/O PH2/COL J12 I/O PH14/COL K1 I/O PD5/ROW K2 I/O PD0/ROW K3 I/O PD7/ROW K4 I/O PD9/ROW K5 I/O PC6/ROW K6 I/O PC13/ROW K7 I/O NRST K8 I/O PB3/SPI2_NSS/COL/JTDO/TRACESWO K9 I/O PH8/COL K10 I/O PH9/COL K11 I/O PH11/COL K12 I/O PH15/COL L1 I/O PD6/ROW ...

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... STM32TS60 Table 3. STM32TS60 pin definitions (continued) Pin Pin Pin (1)(2) (3) no. type level L11 I/O PH4/COL L12 I/O PH12/COL M1 I/O PD8/ROW M2 I/O PD10/ROW M3 I/O PD13/ROW M4 I/O PD15/ROW M5 I/O PC7/ROW M6 S VDD_2 M7 S VSS_2 M8 I/O PB5/TIM2_ETR/TRACECLK/COL M9 I/O PH1/COL M10 I/O PH5/COL M11 I/O PH6/COL M12 I/O PH3/COL input pin output push-pull, I/O = input/output output open drain supply pin 2 ...

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... SRAM 0x0 801 FFF F Code Flash memory 0x0 800 000 0 Aliased to Flash or system memory depending on BOOT pins 0x0000 0000 Not used/Reserved Doc ID 16925 Rev 3 STM32TS60 0x6000 0000 Reserved 0x4002 3400 CRC 0x4002 3000 Reserved 0x4002 2400 Flash interface 0x4002 2000 Reserved ...

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... STM32TS60 5 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ® ECOPACK trademark. Figure 4. UFBGA144 - ultra low profile fine pitch ball grid array package ...

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... Doc ID 16925 Rev 3 STM32TS60 (1) inches Typ Min Max 0.0209 0.0181 0.0236 0.0031 0.0024 0.0039 0.0177 0.0157 0.0197 0.0051 0.0031 0.0071 0.0126 0.0106 ...

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... The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Table 6. Ordering information for die devices Die part number STM32TS60DIE1 STM32 Memory (Kbytes) Package 32 Unsawn wafer ...

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... SPI2_NSS pin, and added footnote. Passive component list footnotes. Added Section 5: Package Renamed Section 6: Ordering The STM32TS60 is no longer an ASIC MCU but a standard STM32 MCU. Consequently, the title of this document has been changed and the Features and edited. Added ...

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... STM32TS60 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...