ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet

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ST10F273Z4

Manufacturer Part Number
ST10F273Z4
Description
16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST10F273Z4

Single Voltage Supply
5 V ±10%

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ST10F273Z4Q3
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ST10F273Z4Q3
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Features
Table 1.
January 2008
ST10F273Z4Q3
ST10F273Z4T3
Part Number
High performance 16-bit CPU with DSP
functions
– 31.25 ns instruction cycle time at 64 MHz
– Multiply/accumulate unit (MAC) 16 x 16-bit
– Enhanced boolean bit manipulations
– Single-cycle context switching support
Memory organization
– 512 Kbyte on-chip Flash memory single
– 100K erasing/programming cycles.
– Up to 16 Mbyte linear address space for
– 2 Kbyte on-chip internal RAM (IRAM)
– 34 Kbyte on-chip extension RAM (XRAM)
– Programmable external bus configuration &
– 5 programmable chip-select signals
– Hold-acknowledge bus arbitration support
Interrupt
– 8-channel peripheral event controller for
– 16-priority-level interrupt system with 56
Timers
– 2 multifunctional general purpose timer
Two 16-channel capture / compare units
4-channel PWM unit + 4-channel XPWM
max CPU clock
multiplication, 40-bit accumulator
voltage with erase/program controller (full
performance, 32-bit fetch)
code and data (5 Mbytes with CAN or I
characteristics for different address ranges
single cycle interrupt driven data transfer
sources, sampling rate down to 15.6 ns
units with 5 timers
16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
Device summary
PQFP144
LQFP144
Package
frequency
Max CPU
64 MHz
40 MHz
2
C)
512 KB
512 KB
Iflash
Rev 2
PQFP144 (28 x 28 x 3.4mm)
(Plastic Quad Flat Package)
A/D Converter
– 24-channel 10-bit
– 3 µs Minimum conversion time
Serial channels
– 2 synch. / asynch. serial channels
– 2 high-speed synchronous channels
– I
2 CAN 2.0B interfaces operating on 1 or 2 CAN
busses (64 or 2x32 messages, C-CAN version)
Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
On-chip bootstrap loader
Clock generation
– On-chip PLL and 4 to 12 MHz oscillator
– Direct or prescaled clock input
Real-time clock and 32 kHz on-chip oscillator
Up to 111 general purpose I/O lines
– Individually programmable as input, output
– Programmable threshold (hysteresis)
Idle, power down and stand-by modes
Single voltage supply: 5 V ±10%.
Xflash
or special function
No
No
2
C standard interface
36 KB
36 KB
RAM
ST10F273Z4
(Low Profile Quad Flat Package)
Temperature range (°C)
LQFP144 (20 x 20 x 1.4mm)
-40/+125
-40/+125
www.st.com
1/188
1

Related parts for ST10F273Z4

ST10F273Z4 Summary of contents

Page 1

... Idle, power down and stand-by modes ■ Single voltage supply ±10%. Max CPU Iflash Xflash frequency 64 MHz 512 MHz 512 KB No Rev 2 ST10F273Z4 LQFP144 ( 1.4mm) (Low Profile Quad Flat Package) RAM Temperature range (° -40/+125 36 KB -40/+125 1/188 www.st.com 1 ...

Page 2

... Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . 37 Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . 37 Flash non volatile access protection register Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 38 Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . 38 ST10F273Z4 ...

Page 3

... ST10F273Z4 5.5.7 5.5.8 5.5.9 5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 44 6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 Alternate and selective boot mode (ABM & SBM 6.3.1 6.3.2 6.3.3 7 Central processing unit (CPU 7.1 Multiplier-accumulator unit (MAC 7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8 External bus controller ...

Page 4

... Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 20.3 Synchronous reset (warm reset 20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4/188 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ST10F273Z4 ...

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... ST10F273Z4 21.2.1 21.2.2 21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 21.3.1 21.3.2 21.3.3 21.3.4 22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 110 23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 23.2 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 24 ...

Page 6

... External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 24.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 24.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 172 25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 6/188 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 ST10F273Z4 ...

Page 7

... ST10F273Z4 List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3. Address space of the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4. Flash modules sectorization (read operations Table 5. Flash modules sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9 ...

Page 8

... Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 79. CLKOUT and READY timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 80. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 81. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 82. SSC slave mode timings 174 Table 83. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 8/188 = 5V ± ST10F273Z4 = –40°C to +125° 151 ...

Page 9

... ST10F273Z4 List of figures Figure 1. ST10F273 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. Pin configuration (top view Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 4. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5. CPU block diagram (MAC unit not included Figure 6. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 7. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 8. Block diagram of GPT1 Figure 9. Block diagram of GPT2 Figure 10 ...

Page 10

... External bus arbitration (releasing the bus 170 Figure 58. External bus arbitration (regaining the bus 171 Figure 59. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 60. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 61. 144-pin plastic quad flat package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 62. 144-pin low profile quad flat package (10x10 177 10/188 ST10F273Z4 ...

Page 11

... Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F273Z4 is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work ...

Page 12

... Port5 channels. ● External Memory bus is affected by limitations on maximum speed and maximum capacitance load: ST10F273Z4 is not able to address an external memory at 64 MHz with 0 wait states. ● XPERCON register bit mapping modified according to new peripherals implementation (not fully compatible with ST10F269). ● ...

Page 13

... ST10F273Z4 Figure 1. ST10F273Z4 Logic symbol V18 VDD VSS XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT VAREF VAGND ST10F273Z4 NMI EA / VSTBY READY ALE WRL Port 5 16-bit Introduction Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 ...

Page 14

... ST10F273Z4 ST10F273Z4 108 P0H.0 / AD8 107 P0L.7 / AD7 106 P0L.6 / AD6 105 P0L.5 / AD5 104 P0L.4 / AD4 103 P0L.3 / AD3 102 P0L.2 / AD2 101 P0L.1 / AD1 100 P0L.0 / AD0 VSTBY ...

Page 15

... ST10F273Z4 Table 2. Pin description Symbol Pin Type I ... ... 5 O P6 I/O 9-16 I/O I ... ... I/O P8 I/O 14 I/O I/O 15 I/O I 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers ...

Page 16

... CC0IO CAPCOM: CC0 capture input/compare output ... ... ... P2.7 CC7IO CAPCOM: CC7 capture input/compare output P2.8 CC8IO CAPCOM: CC8 capture input/compare output EX0IN Fast external interrupt 0 input ... ... ... P2.15 CC15IO CAPCOM: CC15 capture input/compare output EX7IN Fast external interrupt 7 input T7IN CAPCOM2: timer T7 count input ST10F273Z4 Function ...

Page 17

... ST10F273Z4 Table 2. Pin description (continued) Symbol Pin Type 65-70, I/O 73-80, I P3 P3.6 - P3.13, P3. I 15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers ...

Page 18

... Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. ST10F273Z4 Function ...

Page 19

... I External access enable pin. A low level applied to this pin during and after Reset forces the ST10F273Z4 to start the program from the external memory space. A high level forces ST10F273Z4 to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F273Z4 under reset and main V ...

Page 20

... NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F273Z4 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode ...

Page 21

... ST10F273Z4 3 Functional description The architecture of the ST10F273Z4 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F273Z4. Figure 3. Block diagram XRAM 16 2K ...

Page 22

... Memory organization 4 Memory organization The memory space of the ST10F273Z4 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed Byte wise or Word wise. Particular portions of the on-chip memory have additionally been made directly bit addressable ...

Page 23

... ST10F273Z4 interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The XRAM2 address range is F’0000h-F’7FFFFh if XPEN (bit 2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. The lower portion of the XRAM2 (address range F’ ...

Page 24

... Mbytes of external memory can be connected to the microcontroller. Visibility of XBUS peripherals In order to keep the ST10F273Z4 compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the ...

Page 25

... ST10F273Z4 5 Internal Flash memory 5.1 Overview The on-chip Flash is composed by one matrix module divided in two banks that can be read and modified indipendently one of the other: one bank can be read while another bank is under modification. Bank 0 is 384 Kbytes wide, Bank 1 is 128 Kbytes wide. ...

Page 26

... FFFF 0x0003 0000 - 0x0003 FFFF 0x0004 0000 - 0x0004 FFFF 0x0005 0000 - 0x0005 FFFF 0x0006 0000 - 0x0006 FFFF 0x0007 0000 - 0x0007 FFFF 0x0008 0000 - 0x0008 FFFF ST10F273Z4 operations)) and when accessed in write Size ST10 Bus size ...

Page 27

... ST10F273Z4 Table 6. Flash modules sectorization Bank Bank 0 Test-Flash (B0TF) Bank 0 Flash 0 (B0F0) Bank 0 Flash 1 (B0F1) Bank 0 Flash 2 (B0F2) Bank 0 Flash 3 (B0F3) B0 Bank 0 Flash 4 (B0F4) Bank 0 Flash 5 (B0F5) Bank 0 Flash 6 (B0F6) Bank 0 Flash 7 (B0F7) Bank 0 Flash 8 (B0F8) Bank 0 Flash 9 (B0F9) Bank 1 Flash 0 (B1F0) ...

Page 28

... Flash Control Registers. 28/188 Description 0x000E 0000 - 0x000E 0007 0x000E 0008 - 0x000E 000F 0x000E 0010 - 0x000E 0013 0x000E 0014 - 0x000E 0015 0x000E DFB4 - 0x000E DFB7 0x000E DFB8 - 0x000E DFB9 0x000E DFBC - 0x000E DFBF ST10F273Z4 Addresses Size 8 byte 8 byte 4 byte 2 byte 16-bit (XBUS) 4 byte ...

Page 29

... ST10F273Z4 Power supply drop If, during a write operation, the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to Read mode. At following Power-on, the interrupted Flash write operation must be repeated. 5.4 Register description 5 ...

Page 30

... FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation. 30/188 FCR SER reserved SPR SMOD Function ST10F273Z4 Reset Value: 0000h reserved 0 ...

Page 31

... ST10F273Z4 Table 9. Flash control register 0 high (continued) Bit Suspend This bit must be set to suspend the current Program (Word or Double Word) or Sector Erase operation in order to read data in one of the sectors of the bank under modification or to program data in another bank. The Suspend operation resets the Flash bank to normal read mode (automatically resetting bits BSYx) ...

Page 32

... B1S B0S RS RS Function Table 12 Banks (BxS) and Sectors (BxFy) Status bits Table 12 Banks (BxS) and Sectors (BxFy) Status bits BxS = 1 meaning ST10F273Z4 Reset value: 0000h reserved B1F1 B1F0 RS BxFy = 1 meaning Erase error in sector y of bank x Erase suspended in sector y of bank x Don’ ...

Page 33

... ST10F273Z4 5.4.5 Flash data register 0 low The Flash Address Registers (FARH/L) and the Flash Data Registers (FDR1H/L-FDR0H/L) are used during the program operations to store Flash Address in which to program and Data to program. FDR0L (0x0E 0008 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 ...

Page 34

... Function FCR Function Reset value: FFFFh Reset value: FFFFh Reset value: 0000h ST10F273Z4 reserved ...

Page 35

... ST10F273Z4 5.4.10 Flash address register high FARH (0x0E 0012 reserved Table 18. Flash address register high Bit Address 20:16 ADD(20:16) These bits must be written with the Address of the Flash location to program in the following operations: Word Program and Double Word Program. 5.4.11 Flash error register Flash Error register, as well as all the other Flash registers, can be properly read only once LOCK bit of register FCR0L is low ...

Page 36

... The 5 Non Volatile Protection Registers are one time programmable for the user. Two register (FNVWPIRL/FNVWPIRH) are used to store the Write Protection fuses for each sector IFlash module. The other three Registers (FNVAPR0 and FNVAPR1L/H) are used to store the Access Protection fuses. 36/188 Function ST10F273Z4 ...

Page 37

... ST10F273Z4 5.5.2 Flash non volatile write protection I register low FNVWPIRL (0x0E DFB4 reserved Table 20. Flash non volatile write protection register low Bit Write protection bank 0 / sectors 9-0 W0P(9:0) These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFlash). 5.5.3 Flash non volatile write protection I register high ...

Page 38

... NVR Function NVR Function ST10F273Z4 Delivery value: FFFFh Delivery value: FFFFh ...

Page 39

... ST10F273Z4 memory as listed in the first column, what is possible and what is not possible to do (see column headers) is shown in the table. Table 25. Summary of access protection level Fetching from IFlash Fetching from IRAM Fetching from XRAM Fetching from External memory 5.5.8 Write protection The Flash modules have one level of Write Protections: Each sector of each bank can be Software Write Protected by programming at 0 the related bit WyPx in FNVWPIRL/H register ...

Page 40

... DWPG, SMOD must be set/ /*Load Add in FARL*/ /*Load Add in FARH*/ /*Load Data in FDR0L*/ /*Load Data in FDR0H*/ /*Load Data in FDR1L*/ /*Load Data in FDR1H*/ /*Operation start*/ /*Set SER in FCR0H, SMOD must be set*/ /*Set B0F1, B0F0*/ /*Operation start*/ /*Set SUSP in FCR0H*/ ST10F273Z4 ...

Page 41

... ST10F273Z4 Then the operation can be resumed in the following way: FCR0H |= 0x0800; FCR0H |= 0x8000; Before resuming a suspended Erase, FCR1H/FCR1L must be read to check if the Erase is already completed (FCR1H = FCR1L = 0x0000 if Erase is complete). Original setup of Select Operation bits in FCR0H/L must be restored before the operation resume, otherwise the operation is aborted and bit RESER of FER is set ...

Page 42

... Add of register FNVAPR1L in FARL*/ = 0x000E; /*Load Add of register FNVAPR1L in FARH*/ = 0xFFFE; /*Load Data in FDR0L for clearing PDS0*/ /*Operation start*/ /*Set SPR in FCR0H*/ = 0xDFBC; /*Load Add register FNVAPR1H in FARL*/ = 0x000E; /*Load Add register FNVAPR1H in FARH*/ = 0xFFFE; /*Load Data in FDR0H for clearing /*Operation start*/ ST10F273Z4 ...

Page 43

... ST10F273Z4 5.7 Write operation summary In general, each write operation is started through a sequence of 3 steps: 1. The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0. 2. The second step is the definition of the Address and Data for programming or the sectors or banks to erase, SMOD must be always set except for writing in Flash Non Volatile Protection registers ...

Page 44

... Standard bootstrap loader After entering the standard BSL mode and the respective initialization, the ST10F273Z4 scans the RxD0 line and the CAN1_RxD line to receive either a valid dominant bit from CAN interface start condition from UART line. Start condition on UART RxD: ST10F273Z4 starts standard bootstrap loader. This bootstrap loader is identical to other ST10 devices (example: ST10F269, ST10F168) ...

Page 45

... ST10F273Z4 6.3 Alternate and selective boot mode (ABM & SBM) 6.3.1 Activation of the ABM and SBM Alternate boot is activated with the combination ‘01’ on Port0L[5..4] at the rising edge of RSTIN. 6.3.2 User mode signature integrity check The behavior of the Selective Boot mode is based on the computing of a signature between the content of 2 memory locations and a comparison with a reference signature ...

Page 46

... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F273Z4’s instructions can be executed in one instruction cycle which requires 31.25ns at 64 MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted ...

Page 47

... ST10F273Z4 7.1 Multiplier-accumulator unit (MAC) The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms. The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with operands per instruction cycle. ...

Page 48

... Central processing unit (CPU) 7.2 Instruction set summary The Table 28 lists the instructions of the ST10F273Z4. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Table 28. Standard instruction set summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) ...

Page 49

... ST10F273Z4 Table 28. Standard instruction set summary (continued) Mnemonic J(N)B JBC JNBS CALLA, CALLI,CALLR Call absolute/indirect/relative subroutine if condition is met CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative if direct bit is (not) set ...

Page 50

... Central processing unit (CPU) 7.3 MAC coprocessor specific instructions The Table 29 lists the MAC instructions of the ST10F273Z4. The detailed description of each instruction can be found in the “ST10 Family Programming Manual”. Note that all MAC instructions are encoded on 4 bytes. Table 29. MAC instruction set summary ...

Page 51

... ST10F273Z4 8 External bus controller All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four different external memory access modes: ● 16- / 18- / 20- / 24-bit addresses and 16-bit data, demultiplexed ● ...

Page 52

... When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. The ST10F273Z4 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. ...

Page 53

... ST10F273Z4 Table 30. Interrupt sources (continued) Source of Interrupt or PEC Service Request CAPCOM register 6 CAPCOM register 7 CAPCOM register 8 CAPCOM register 9 CAPCOM register 10 CAPCOM register 11 CAPCOM register 12 CAPCOM register 13 CAPCOM register 14 CAPCOM register 15 CAPCOM register 16 CAPCOM register 17 CAPCOM register 18 CAPCOM register 19 CAPCOM register 20 CAPCOM register 21 ...

Page 54

... XP2IE XP2INT XP3IR XP3IE XP3INT 2 C, PWM1 and RTC need some resources to implement interrupt Figure 7, the principle is explained through a simple XIRxSEL[15:8] Interrupt Enable bits XIRxSEL[7:0] Interrupt Flag bits ST10F273Z4 Vector Trap Location Number 00’0098h 26h 00’009Ch 27h 00’00A0h 28h 00’00A4h 29h 00’ ...

Page 55

... ST10F273Z4 When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL register) define a mask which controls which sources will be associated with the unique available vector. If more than one source is enabled to issue the request, the service routine will have to take care to identify the real event to be serviced. This can easily be done by checking the flag bits (Byte Low of XIRxSEL register) ...

Page 56

... MACTRP BTRAP 00’0028h PRTFLT BTRAP 00’0028h ILLOPA BTRAP 00’0028h ILLINA BTRAP 00’0028h ILLBUS BTRAP 00’0028h [002Ch - 003Ch] Any 0000h – 01FCh in steps of 4h ST10F273Z4 XP2INT XP3INT (1) Trap Trap number priority 00h III 00h III 00h III 02h II 04h ...

Page 57

... ST10F273Z4 10 Capture / compare (CAPCOM) units The ST10F273Z4 has two 16-channel CAPCOM units which support generation and control of timing sequences channels with a maximum resolution of 125ns at 64 MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events ...

Page 58

... ST10F273Z4 111b 1024 39.1 kHz 25.6µs 1.678s 111b 1024 64 kHz 16.0µs 1.049s ...

Page 59

... ST10F273Z4 11 General purpose timer unit The GPT unit is a flexible multifunctional timer/counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...

Page 60

... T2 mode Reload control Capture T3 mode control Capture Reload T4 mode control ST10F273Z4 100b 101b 110b 128 256 512 500 kHz 250 kHz 128 kHz 2.0 µs 4.0 µs 8.0 µs U/D Interrupt GPT1 timer T2 request T3OUT T3OTL ...

Page 61

... ST10F273Z4 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) ...

Page 62

... Figure 9. Block diagram of GPT2 T5EUD CPU clock 2n n=2...9 T5IN CAPIN T6IN CPU clock 2n n=2...9 T6EUD 62/188 U/D T5 GPT2 timer T5 mode control Clear Capture GPT2 CAPREL T6 GPT2 timer T6 mode control U/D ST10F273Z4 Interrupt request Interrupt request Reload Interrupt request Toggle FF T60TL T6OUT to CAPCOM timers ...

Page 63

... ST10F273Z4 12 PWM modules Two pulse width modulation modules are available on ST10F273Z4: standard PWM0 and XBUS PWM1. They can generate up to four PWM output signals each, using edge-aligned or centre-aligned PWM. In addition, the PWM modules can generate PWM burst signals and single shot outputs. The resolutions ...

Page 64

... Parallel ports 13.1 Introduction The ST10F273Z4 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F273Z4 has nine groups of I/O lines gathered as follows: ● Port two time 8-bit port named P0L (Low as less significant byte) and P0H (high as most significant byte) ● ...

Page 65

... Open Drain Control Registers ODPx. 13.2.2 Input threshold control The standard inputs of the ST10F273Z4 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS input thresholds can be selected instead of the standard TTL thresholds for all the pins. These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds ...

Page 66

... All port lines that are not used for these alternate functions may be used as general purpose I/O lines. 66/188 ST10F273Z4 ...

Page 67

... The ST10F273Z4 has 16+8 multiplexed input channels on Port 5 and Port 1. The selection between Port 5 and Port 1 is made via a bit in a XBus register. Refer to the User Manual for a detailed description. ...

Page 68

... CPU clock cycles. During this time, the busy flag ADBSY is set to indicate the operation. It compensates the capacitance mismatch, so the calibration procedure does not need any update during normal operation. No conversion can be performed during this time: the bit ADBSY shall be polled to verify when the calibration is over, and the module is able to start a convertion. 68/188 ST10F273Z4 ...

Page 69

... SSC1 (XBUS mapped). 15.1 Asynchronous / synchronous serial interfaces The asynchronous / synchronous serial interfaces (ASC0 and ASC1) provides serial communication between the ST10F273Z4 and other microcontrollers, microprocessors or external peripherals. 15.2 ASCx in asynchronous mode In asynchronous mode 9-bit data transfer, parity generation and the number of stop bits can be selected ...

Page 70

... The deviation errors given in the errors use a Baud rate crystal (providing a multiple of the ASC0 sampling frequency). 15.3 ASCx in synchronous mode In synchronous mode, data is transmitted or received synchronously to a shift clock which is generated by the ST10F273Z4. Half-duplex communication Baud (at 40 MHz possible in this mode. CPU Table 44. ...

Page 71

... High speed synchronous serial interfaces The High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) provides flexible high- speed serial communication between the ST10F273Z4 and other microcontrollers, microprocessors or external peripherals. The SSCx supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSCx itself (master mode received from an external master (slave mode) ...

Page 72

... Baud 4M Baud 1M Baud 100K Baud 10K Baud 1K Baud 489 Baud 72/188 Baud rate = 32 MHz (or lower) CPU Baud rate = 32 MHz (or lower) CPU = 48 MHz (or lower) CPU ST10F273Z4 = 40 MHz) CPU Bit time Reload value --- 0000h --- 0001h 150ns 0002h 200ns 0003h 400ns 0007h 1µs 0013h 10µ ...

Page 73

... ST10F273Z4 interface 2 The integrated I C Bus Module handles the transmission and reception of frames over the two-line SDA/SCL in accordance with the I operate in slave mode, in master mode or in multi-master mode. It can receive and transmit data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s ...

Page 74

... The user is also allowed to map internally both CAN modules on the same pins P4.5 and P4.6. In this way, P4.4 and P4.7 may be used either as general purpose I/O lines, or used 2 for I C interface. This is possible by setting bit CANPAR of XMISC register. To access this register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register. 74/188 22. ST10F273Z4 ...

Page 75

... CAN bus configurations Depending on application, CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F273Z4 is able to support these two cases. Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 11 ...

Page 76

... CAN modules Multiple CAN bus The ST10F273Z4 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 13. Figure 13. Connection to two different CAN buses (e.g. for gateway application) CAN_H CAN_L Parallel mode In addition to previous configurations, a parallel mode is supported. This is shown in Figure 14. ...

Page 77

... ST10F273Z4 18 Real-time clock The real-time clock is an independent timer, in which the clock is derived directly from the clock oscillator on XTAL1 (main oscillator) input or XTAL3 input (32 kHz low-power oscillator) so that it can be kept on running even in idle or power down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed with the following characteristics: ● ...

Page 78

... MHz and 64 MHz CPU = 40 MHz) CPU 2 (WDTIN = ‘0’) 12.8µs 3.277ms = 64 MHz) CPU 2 (WDTIN = ‘0’) 8µs 2.048ms Prescaler for MHz CPU 128 (WDTIN = ‘1’) 819.2µs 209.7ms Prescaler for MHz CPU 128 (WDTIN = ‘1’) 512µs 131.1ms ST10F273Z4 ...

Page 79

... ST10F273Z4 20 System reset System reset initializes the MCU in a predefined state. There are six ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 50. Reset event definition Reset Source Power-on reset Asynchronous hardware reset Synchronous long hardware ...

Page 80

... Electrical Characteristics Section), with an already stable V of the ST10F273Z4 does not need a stabilized clock signal to detect an asynchronous reset suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Port0 is settled ...

Page 81

... ST10F273Z4 In next Figures 15 respectively with boot from internal or external memory, highlighting the reset phase extension introduced by the embedded FLASH module when selected. Note: Never power the device without keeping RSTIN pin grounded: the device could enter in unpredictable states, risking also permanent damages. ...

Page 82

... PLL stabilization) ≤ 10.2 ms (for crystal oscillation + PLL stabilization) ≥ (for on-chip VREG stabilization) ≤ 2 TCL ... ≥ ≤ 500 ns 3..4 TCL transparent not t. transparent not transparent ≤ Latching point of Port0 for system start-up configuration ST10F273Z4 not t. not t. not t. 7 TCL ...

Page 83

... ST10F273Z4 Figure 16. Asynchronous power-on RESET ( XTAL1 RPD RSTIN RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST TCL d Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggered by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 28, It occurs when RSTIN is low and RPD is detected (or becomes) low as well ...

Page 84

... Input Filter on RSTIN pin 84/188 1) ≥ ≤ 500 ns ≥ ≤ 500 ns transparent not transparent not transparent transparent not transparent ST10F273Z4 ≤ 2 TCL 3..4 TCL not t. not t. not t. not t. 7 TCL ≤ Latching point of Port0 for system start-up configuration ...

Page 85

... FLASH is used, the restarting occurs after the embedded FLASH initialization routine is completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F273Z4 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 86

... FLASH initialization when EA=1 (internal memory selected). Then, the code execution restarts. The system configuration is latched from Port0, and ALE, RD and WR/WRL pins are driven to their inactive level. The ST10F273Z4 starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine ...

Page 87

... ST10F273Z4 fact that it can degenerate into Long Reset: the two figures show the behavior when booting from internal or external memory respectively. Figures typical synchronous Long Reset, again when booting from internal or external memory. Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low (by external hardware consequence of a Bidirectional reset), the RPD internal weak pull-down is activated ...

Page 88

... TCL 1) 3) ≥ ≤ 500 ns ≤ 500 ns not transparent not t. transparent not transparent 1024 TCL 200µA Discharge ST10F273Z4 ≥ ≤ 2 TCL not t. not t. 7 TCL ≤ TCL At this time RSTF is sampled HIGH or LOW SHORT or LONG reset 2) V > ...

Page 89

... ST10F273Z4 Figure 20. Synchronous short / long hardware RESET ( ≤4 TCL RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD 1) RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered ...

Page 90

... TCL At this time RSTF is sampled LOW definitely LONG reset 200µA Discharge Section 21.1). ST10F273Z4 ≤ 2 TCL 3..4 TCL not t. not t. not t. 7 TCL ≤ > 2.5V Asynchronous reset RPD not entered ...

Page 91

... ST10F273Z4 Figure 22. Synchronous long hardware RESET ( RSTIN ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:2] P0[1:0] ALE RST RSTOUT RPD 1) If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 2) Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21 ...

Page 92

... FLARST RST RSTOUT 92/188 23 and 24 for unidirectional SW reset timing, and to Figures 25, 23 and 24 for unidirectional SW reset timing, and to Figures 25, not transparent transparent not transparent not transparent 1024 TCL ST10F273Z4 26 26 ≤ 2 TCL not t. not t. 7 TCL ≤ and and ...

Page 93

... ST10F273Z4 Figure 24 WDT unidirectional RESET ( RSTIN P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 20.6 Bidirectional reset As shown in the previous sections, the RSTOUT pin is driven active (low level) at the beginning of any reset sequence (synchronous/asynchronous hardware, software and watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization routine, until the protected EINIT instruction (End of Initialization) is completed ...

Page 94

... FLASH itself extend the internal reset duration well beyond the filter delay. Next Figures 25, Bidirectional reset events: In particular reset. 94/188 26 and 27 summarize the timing for Software and Watchdog Timer Figure 27 ST10F273Z4 shows the degeneration into Hardware ...

Page 95

... ST10F273Z4 Figure 25 WDT bidirectional RESET (EA=1) RSTIN RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] IBUS-CS (Internal) FLARST RST RSTOUT ≥ ≥ ≤ 500 ns ≤ 500 ns not transparent transparent not transparent not transparent ≤ 1024 TCL System reset not t. not t. ≤ 2 TCL 7 TCL ...

Page 96

... Figure 26 WDT bidirectional RESET ( RSTIN ≥ ≤ 500 ns RSTF (After Filter) P0[15:13] P0[12:8] P0[7:2] P0[1:0] ALE RST RSTOUT 96/188 ≥ ≤ 500 ns not transparent transparent not transparent not transparent 1024 TCL At this time RSTF is sampled HIGH WDT Reset is flagged in WDTCON ST10F273Z4 not t. not t. 8 TCL ...

Page 97

... If bit PWDCFG of SYSCON register is set, an internal pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any capacitor connected on RPD pin. The simplest way to reset the ST10F273Z4 is to insert a capacitor C1 between RSTIN pin and V , and a capacitor between RPD pin and V ...

Page 98

... Figure 28. Minimum external reset circuitry The minimum reset circuit of the ST10F273Z4 itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above V reset sequence, and thus will trigger an asynchronous reset sequence. Figure 29 shows an example of a reset circuit. In this example, R1-C1 external circuit is only used to generate power-up or manual reset, and R0-C0 circuit on RPD is used for power-up reset and to exit from Power down mode ...

Page 99

... ST10F273Z4 Figure 29. System reset circuit ST10F273Z4 Figure 30. Internal (simplified) reset circuitry Internal reset signal External hardware RSTIN o.d. R0 Open drain inverter RPD + C0 EINIT Instruction Clr Q Set Reset state machine clock SRST instruction Trigger watchdog overflow Clr Reset Sequence (512 CPU clock cycles) ...

Page 100

... Next two timing diagrams bidirectional internal reset events (Software and Watchdog) including in particular the external capacitances charge and discharge transients (refer also to external circuit scheme). Figure 31. Example of software or watchdog bidirectional reset ( 100/188 (Figure 31 and Figure 32) provides additional examples of ST10F273Z4 Figure 29 for the ...

Page 101

... ST10F273Z4 Figure 32. Example of software or watchdog bidirectional reset ( System reset 101/188 ...

Page 102

... Activated by internal logic for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic only for 1024 TCL 1032 + 12 TCL + max(4 TCL, 500ns) Activated by internal logic only for 1024 TCL ST10F273Z4 WDTCON Flags - ...

Page 103

... ST10F273Z4 Table 51. Reset event (continued) Event Synch Synch. (2) Software reset Synch Synch Synch Synch. (2) Watchdog reset Synch Synch can degenerate into a Long Hardware Reset and consequently differently flagged (see 2. When Bidirectional is active (and with RPD=0), it can be followed by a Short Hardware Reset and consequently differently flagged (see Section 20 ...

Page 104

... P0L.7 ROMEN BYTDIS 104/188 PORT0 H.4 H.3 H.2 H.1 H.0 L.7 L.6 SALSEL CSSEL WRC BUSTYP CSSEL WRC SALSEL Bootstrap Loader Port 4 Port 6 2 Logic Logic P0L.7 SYSCON BUS WRCFG ACT0 7 10 ST10F273Z4 L.5 L.4 L.3 L.2 L.1 L.0 BSL Res. ADP EMU Internal Control Logic BUSCON0 ALE BTYP CTL0 VSTBY ...

Page 105

... Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F273Z4. In Idle mode only CPU is stopped, while peripheral still operate. In Power down mode both CPU and peripherals are stopped. In Stand-by mode the main power supply (V ...

Page 106

... A dedicated embedded low-power voltage regulator is implemented to generate the internal low voltage supply (about 1.65V in Stand-by mode) to bias all those circuits that shall remain active: the portion of XRAM (16Kbytes for ST10F273Z4), the RTC counters and 32 kHz on- chip oscillator amplifier. 106/188 ...

Page 107

... V 18SB from ST10F273Z4 Core (active low signal) is low enough to be recognized as a logic “0” by the RAM interface (due to V address for the RAM and an unwanted data corruption could occur. For this reason, an extra interface, powered by the switched supply, is used to prevent the RAM from this kind of potential corruption mechanism ...

Page 108

... During power-off phase important that the external hardware maintains a stable ground level on RSTIN pin, without any glitch, in order to avoid spurious exiting from reset status with unstable power supply. STBY ST10F273Z4 pin external voltage). becomes higher than about 1.0V, there 18 ), the Real-Time Clock ...

Page 109

... ST10F273Z4 21.3.4 Power reduction modes summary In the following Table 53: Power reduction modes Power reduction modes is reported. Table 53. Power reduction modes summary Mode Idle Power down Stand- off off off off on on off off on on off off off on off off ...

Page 110

... SYSCON possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed. 110/188 ST10F273Z4 ...

Page 111

... This section summarizes all registers implemented in the ST10F273Z4, ordered by name. 23.1 Special function registers The following table lists all SFRs which are implemented in the ST10F273Z4 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “ ...

Page 112

... CAPCOM register 17 interrupt control register 32h CAPCOM register 18 B2h CAPCOM register 18 interrupt control register 33h CAPCOM register 19 B3h CAPCOM register 19 interrupt control register 34h CAPCOM register 20 B4h CAPCOM register 20 interrupt control register ST10F273Z4 Reset value 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h 0000h - - 00h ...

Page 113

... ST10F273Z4 Table 54. List of special function registers (continued) Physical Name address CC21 FE6Ah CC21IC b F16Ah E CC22 FE6Ch CC22IC b F16Ch E CC23 FE6Eh CC23IC b F16Eh E CC24 FE70h CC24IC b F170h E CC25 FE72h CC25IC b F172h E CC26 FE74h CC26IC b F174h E CC27 FE76h CC27IC b F176h E CC28 FE78h CC28IC ...

Page 114

... MAC unit repeat word EFh MAC unit status word E1h Port 2 open drain control register E3h Port 3 open drain control register E5h Port 4 open drain control register E7h Port 6 open drain control register ST10F273Z4 Reset value - - 00h - - 00h - - 00h 0000h 0000h - - 00h - - 00h - - 00h ...

Page 115

... ST10F273Z4 Table 54. List of special function registers (continued) Physical Name address ODP7 b F1D2h E ODP8 b F1D6h E ONES b FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h P1H b FF06h P2 b FFC0h P3 b FFC4h P4 b FFC8h P5 b FFA2h P6 b FFCCh P7 b FFD0h P8 b FFD4h P5DIDIS b FFA4h PECC0 ...

Page 116

... CPU stack underflow pointer register 89h CPU system configuration register 28h CAPCOM timer 0 register A8h CAPCOM timer 0 and timer 1 control register CEh CAPCOM timer 0 interrupt control register 2Ah CAPCOM timer 0 reload register ST10F273Z4 Reset value 0000h 0000h 0000h 0000h 0000h - - 00h 0000h 0000h ...

Page 117

... ST10F273Z4 Table 54. List of special function registers (continued) Physical Name address T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC b FF66h T6 FE48h T6CON b FF48h T6IC b FF68h T7 F050h ...

Page 118

... XPnIR bits (of XPnIC register) of the unused X-Peripheral nodes. 23.2 X-registers The following table lists all X-Bus registers which are implemented in the ST10F273Z4 ordered by their name. The FLASH control registers are listed in a separate section, in spite of they also are physically mapped on X-Bus memory space. Note that all X-Registers are not bit-addressable ...

Page 119

... ST10F273Z4 Table 55. List of XBus registers (continued) Name CAN1IF2CR CAN1IF2DA1 CAN1IF2DA2 CAN1IF2DB1 CAN1IF2DB2 CAN1IF2M1 CAN1IF2M2 CAN1IF2MC CAN1IP1 CAN1IP2 CAN1IR CAN1MV1 CAN1MV2 CAN1ND1 CAN1ND2 CAN1SR CAN1TR CAN1TR1 CAN1TR2 CAN2BRPER CAN2BTR CAN2CR CAN2EC CAN2IF1A1 CAN2IF1A2 CAN2IF1CM CAN2IF1CR CAN2IF1DA1 CAN2IF1DA2 CAN2IF1DB1 CAN2IF1DB2 CAN2IF1M1 CAN2IF1M2 CAN2IF1MC ...

Page 120

... I2C status register 1 EA04h I2C status register 2 ED14h RTC alarm register high byte ED12h RTC alarm register low byte ED00H RTC control register ED0Ch RTC divider counter high byte ST10F273Z4 Reset value 0000h 0000h 0000h 0001h 0000h 0000h 0000h 0000h FFFFh ...

Page 121

... ST10F273Z4 Table 55. List of XBus registers (continued) Name RTCDL RTCH RTCL RTCPH RTCPL XCLKOUTDIV XEMU0 XEMU1 XEMU2 XEMU3 XIR0CLR XIR0SEL XIR0SET XIR1CLR XIR1SEL XIR1SET XIR2CLR XIR2SEL XIR2SET XIR3CLR XIR3SEL XIR3SET XMISC XP1DIDIS XPEREMU XPICON XPOLAR XPP0 XPP1 XPP2 XPP3 XPT0 XPT1 XPT2 ...

Page 122

... XSSC control register E804h XSSC clear control register (write only) E802h XSSC set control register (write only) E880h XSSC port control register E808h XSSC receive buffer E806h XSSC transmit buffer ST10F273Z4 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 123

... A chip identifier with its revision ● A internal Flash and size identifier ● Programming voltage description Note: The ST10F273Z4 device is a commercial version based on the ST10F276E silicon, the identification registers provide the values corresponding to the ST10F276E device. Physical address 0x000E 0012 Flash address register - high ...

Page 124

... MEMSIZE Internal memory size (MEMSIZE) (in Kbyte) 0D0h for 832 Kbytes (ST10F276E) Internal memory type ‘0h’: ROM-Less ‘1h’: (M) ROM memory MEMTYP ‘2h’: (S) Standard Flash memory ‘3h’: (H) High performance Flash memory (ST10F273Z4) ‘4h...Fh’: Reserved 124/188 ESFR ...

Page 125

... IDMEM ● IDPROG ESFR PROGVPP R voltage DD voltage when programming EPROM or FLASH devices is calculated using the = 20 x [PROGVDD] / 256 (volts) - 40h for ST10F273Z4 (5V). DD voltage (no need of external V PP 0403h 114xh (x = silicon revision) F0D0h 0040h Reset Value: 0040h ...

Page 126

... Parameter pins with respect to ground (V DD pin with respect to ground (V STBY pins with respect to ground (V AREF pins with respect to ground (V AGND SS ) must not exceed the values defined by the SS ST10F273Z4 Values ) -0 -0 ...

Page 127

... ST10F273Z4 24.2 Recommended operating conditions Table 62. Recommended operating conditions Symbol V Operating supply voltage DD V Operationg stand-by supply voltage STBY V Operating analog reference voltage AREF T Ambient temperature under bias A T Junction temperature under bias J 1. The value of the V exceed the upper limit (up to 6.0 Volt) for a maximum of 100 hours over the global 300000 hours, representing the lifetime of the device (about 30 years) ...

Page 128

... Where the ST10F273Z4 logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics, is included in the “Symbol” column. Where the external system must provide signals with their respective timing characteristics to the ST10F273Z4, the symbol “SR” for System Requirement, is included in the “Symbol” column. 128/188 Description Ambient temperature range ° ...

Page 129

... ST10F273Z4 24.5 DC characteristics ± 10 Table 65. DC characteristics Symbol Parameter Input low voltage (TTL mode (except RSTIN, EA, NMI, RPD, XTAL1, READY) Input low voltage (CMOS mode ILS (except RSTIN, EA, NMI, RPD, XTAL1, READY Input low voltage RSTIN, EA, NMI, RPD ...

Page 130

... V – = 0.4 V –500 = 0 2.4 V – = 2.4 V – = 0.4 V –500 – –100 – – 1.8 – 0.6 f – – ST10F273Z4 Unit – V – V µA ±0.2 µA ±0.5 +1.0 µA –0.5 µA ±3.0 µA ±1.0 ± –1 250 kΩ µA –40 µ ...

Page 131

... ST10F273Z4 Table 65. DC characteristics (continued) Symbol Parameter Power down supply current I (RTC on, main oscillator on, PD2 main voltage regulator off) Power down supply current I (RTC on, 32 kHz oscillator on, PD3 main voltage regulator off) Stand-by supply current I SB1 (RTC off, oscillators off, V Stand-by supply current ...

Page 132

... Figure 36. Supply current versus the operating frequency (RUN and IDLE modes 132/188 Clock Input Alternate data input latch Test mode Flash sense amplifier and column decoder [MHz] CPU ST10F273Z4 P2.0 CC0IO Output buffer I I CC1 CC2 ...

Page 133

... Word or Double Word Programming time could be longer than the average value. 3. Bank Erase is obtained through a multiple Sector Erase operation (setting bits related to all sectors of the Bank). As ST10F273Z4 implements only one bank, the Bank Erase operation is equivalent to Module and Chip Erase operations. 4. Not 100% tested, guaranteed by Design Characterization ...

Page 134

... Flash data retention characteristics Number of program / erase cycles (-40 °C ≤ T ≤ 125 ° 100 1,000 10,000 100,000 134/188 Data retention time (average ambient temperature 60 °C) 256 Kbyte (code store) > 20 years - - - ST10F273Z4 64 Kbyte (EEPROM emulation) > 20 years > 20 years 10 years 1 year ...

Page 135

... ST10F273Z4 24.7 A/D converter characteristics ± 10 ≤ V ≤ AGND Table 68. A/D converter characteristics Symbol Parameter V SR Analog reference voltage AREF V SR Analog ground voltage AGND V SR Analog input voltage AIN I CC Reference supply current AREF t CC Sample time Conversion time ...

Page 136

... The time that the two different actions during conversion take (sampling, and converting) can be programmed within a certain range in the ST10F273Z4 relative to the CPU clock. The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller ...

Page 137

... ST10F273Z4 Table 69. A/D converter programming (continued) ADST ADCTC Note: The total conversion time is compatible with the formula valid for ST10F269, while the meaning of the bit fields ADCTC and ADSTC is no longer compatible: the minimum conversion time is 388 TCL, which at 40 MHz CPU frequency corresponds to 4 ...

Page 138

... combination of the Offset, Gain and Integral Linearity errors. The different errors may compensate each other depending on the relative sign of the Offset and Gain errors. Refer to 138/188 ) and converts it into 10-bit digital data. The AREF Figure 37): Figure 37, see TUE. ST10F273Z4 Figure 37. (Figure 37, see ...

Page 139

... ST10F273Z4 Figure 37. A/D conversion characteristic 3FF 3FE 3FD 3FC 3FB 3FA Digital 007 out (HEX) 006 005 004 003 002 001 000 1 Offset error OFS 24.7.4 Analog reference pins The accuracy of the A/D converter depends on how accurate is its analog reference: a noise in the reference results in at least that much error in a conversion. A low pass filter on the A/D converter reference source (supplied through pins V in order to clean the signal, minimizing the noise ...

Page 140

... L substantially a switched capacitance, with a frequency where f represents the conversion rate at the considered INTERNAL CIRCUIT SCHEME V DD Channel Sampling selection and Figure 38), in combination L equal to 4pF, a resistance of 1MΩ is ST10F273Z4 5V), AREF ...

Page 141

... ST10F273Z4 (sampled voltage on C must be designed to respect the following relation: The formula above provides a constraints for external network design, in particular on resistive path. A second aspect involving the capacitance network shall be considered. Assuming the three capacitances equivalent circuit reported in Figure 38), when the sampling phase is started (A/D switch close), a charge sharing phenomena is installed ...

Page 142

... The following equation must be A1 already charged ⋅ ⋅ the filter is very high with longer than the sampling time C = conversion rate from the two charge balance equations S ST10F273Z4 F must the S f ...

Page 143

... ST10F273Z4 above simple to derive the following relation between the ideal and real sampled voltage From this formula, in the worst case (when V assuming to accept a maximum error of half a count (~2.44mV immediately evident a constraints the next section an example of how to design the external network is provided, assuming some reasonable values for the internal parameters and making hypothesis on the characteristics of the analog signal to be sampled ...

Page 144

... V The other conditions to be verified is the time constants of the transients are really and significantly shorter than the sampling period duration T For complete set of parameters characterizing the ST10F273Z4 A/D Converter equivalent circuit, refer to Section 24.7: A/D converter characteristics on page ...

Page 145

... ST10F273Z4 24.8 AC characteristics 24.8.1 Test waveforms Figure 41. Input/output waveforms 2.4V 0.4V AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made at VIH Min. for a logic ‘1’ and VIL max for a logic ‘0’. Figure 42. Float waveform VLOAD + 0 ...

Page 146

... Electrical characteristics 24.8.2 Definition of internal timing The internal operation of the ST10F273Z4 is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “ ...

Page 147

... ST10F273Z4 24.8.3 Clock generation modes Next Table 70 associates the combinations of these three bits with the respective clock generation mode. Table 70. On-chip clock generator selections P0.15-13 (P0H.7- The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited MHz input frequency range ...

Page 148

... Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 24.8.6 Oscillator watchdog (OWD) An on-chip watchdog oscillator is implemented in the ST10F273Z4. This feature is used for safety operation with external crystal oscillator (available only when using direct drive mode with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator) ...

Page 149

... Baud rates, etc.) the deviation caused by the PLL jitter is negligible. Refer to next 24.8.8 Voltage controlled oscillator The ST10F273Z4 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. In the following table, a detailed summary of the internal settings and VCO frequency is reported. Table 71. ...

Page 150

... Noise in the PLL loop This contribution again can be caused by the following sources: ● Device noise of the circuit in the PLL ● Noise in supply and substrate. 150/188 is maximum time period of the PLL output clock and T ST10F273Z4 and T , max min is the minimum min and T ...

Page 151

... ST10F273Z4 Device noise of the circuit in the PLL The long term jitter is inversely proportional to the bandwidth of the PLL: the wider is the loop bandwidth, the lower is the jitter due to noise in the loop. Besides, the long term jitter is practically independent on the multiplication factor. The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled Oscillator) ...

Page 152

... Electrical characteristics Figure 44. ST10F273Z4 PLL jitter ±5 ±4 ±3 ±2 ±1 T JIT 0 0 24.8.10 PLL lock / unlock During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the CPU is generated, and the reference clock (oscillator) is automatically disconnected from the PLL input: in this way, the PLL goes into free-running mode, providing the system with a ...

Page 153

... –40 °C to +125 ° Value Min. Max. – 300 – 250 –500 +500 250 2000 500 4000 Value Min. Typ. Max – 0.4 – – 0.25 – DD – ST10F273Z4 Resonator 153/188 Unit µs ps kHz Unit mA ...

Page 154

... SS A Parameter Conditions Start-up (1) Normal run (2) Peak to peak (2) Sine wave middle (2) Stable V DD ST10F273Z4 crystal C A ST10F273Z4 840 Ω 1000 Ω 1180 Ω 580 Ω the package and the stray 0 Value Min. Typ. Max. ...

Page 155

... ST10F273Z4 Table 76. Minimum values of negative resistance (module) for 32 kHz oscillator C = 6pF A 32 kHz - The given values of C printed circuit board: the negative resistance values are calculated assuming additional 5pF to the values in the table. The crystal shunt capacitance (C between XTAL3 and XTAL4 pins is globally assumed equal to 4pF. The external resistance between XTAL3 and XTAL4 is not necessary, since already present on the silicon ...

Page 156

... Note: All external memory bus timings and SSC timings reported in the following tables are granted by design characterization and not fully tested in production. 156/188 t3 t1 VIH2 t2 Symbol ST10F273Z4 t4 VIL2 tOSC Values TCL x [ALECTL] 2TCL x (15 - [MCTC]) 2TCL [MTTC]) ...

Page 157

... ST10F273Z4 24.8.16 Multiplexed bus ± 10 ALE cycle time = 6 TCL + 2t Table 78. Multiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE Address hold after ALE 7 ALE falling edge to RD (with RW-delay) ALE falling edge to RD, WR ...

Page 158

... – 2TCL – – – 16 – 2TCL – – 2TCL – ST10F273Z4 Variable CPU clock 1/2 TCL = MHz Min. Max. – – – – 1.5 ns – TCL + 1.5 ns – ...

Page 159

... ST10F273Z4 Figure 48. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE ALE t 6 CSx A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RD Write cycle Address/data bus (P0) WR WRL WRH Address Address ...

Page 160

... Address/Data Bus (P0) WR WRL WRH 160/188 Address t 7 Address Address ST10F273Z4 Data Data out ...

Page 161

... ST10F273Z4 Figure 50. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS ALE A23-A16 (A15-A8) BHE Read cycle Address/data bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx Address Address ...

Page 162

... Read cycle t 6 Address/Data Bus (P0) RdCSx Write cycle Address/data bus (P0) WrCSx 162/188 Address t 7 Address Address Data Data out ST10F273Z4 ...

Page 163

... ST10F273Z4 24.8.17 Demultiplexed bus ± 10 ALE cycle time = 4 TCL + 2t Table 79. Demultiplexed bus timings Symbol Parameter t CC ALE high time Address setup to ALE 6 Address/Unlatched setup to RD (with RW-delay) Address/Unlatched setup to RD (no RW-delay) RD, WR low time t CC ...

Page 164

... C 0 – – 16 – – 8 – – TCL – 10 ST10F273Z4 Variable CPU Clock 1/2 TCL = MHz Min. Max. – 3TCL – – F – A – A – 2TCL – – 3TCL – – ...

Page 165

... ST10F273Z4 Figure 52. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH Address ...

Page 166

... Data bus (P0) (D15-D8) D7-D0 RD Write cycle Data bus (P0) (D15-D8) D7-D0 WR WRL WRH 166/188 Address Data Data out ST10F273Z4 ...

Page 167

... ST10F273Z4 Figure 54. External memory cycle: demultipl. bus, with/without r/w delay, normal ALE, r/w CS CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx Address Data out ...

Page 168

... A15-A0 (P1) BHE Read cycle Data bus (P0) (D15-D8) D7-D0 RdCSx Write cycle Data bus (P0) (D15-D8) D7-D0 WrCSx 168/188 Address Data Data out ST10F273Z4 ...

Page 169

... ST10F273Z4 24.8.18 CLKOUT and READY ± 10 Table 80. CLKOUT and READY timings Symbol t CC CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time 33 CLKOUT rising edge ALE falling edge ...

Page 170

... The next external bus cycle may start here. 170/188 READY Running cycle 1) wait state ST10F273Z4 MUX / Tri-state order to be safely synchronized. This is ...

Page 171

... Figure 57. External bus arbitration (releasing the bus) CLKOUT HOLD HLDA BREQ CSx (P6.x) Others 1. The ST10F273Z4 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after -40 °C to +125 ° ...

Page 172

... This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F273Z4 requesting the bus. 2. The next ST10F273Z4 driven bus cycle may start here. 172/188 2) ...

Page 173

... ST10F273Z4 24.8.20 High-speed synchronous serial interface (SSC) timing Master mode ±10 Table 82. SSC master mode timings Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time 301 t CC SSC clock low time 302 CC SSC clock rise time ...

Page 174

... The bit timing is repeated for all bits to be transmitted or received. 174/188 300 301 302 t t 304 303 t t 305 305 1st out bit 2nd out bit t t 307 308 2nd In bit 1st in bit ST10F273Z4 305 306 Last out bit t t 307 308 Last in bit ...

Page 175

... ST10F273Z4 Slave mode ±10 Table 83. SSC slave mode timings Symbol t SR SSC clock cycle time 310 SR SSC clock high time t 311 t SR SSC clock low time 312 t SR SSC clock rise time 313 SR SSC clock fall time t 314 Write data valid after shift ...

Page 176

... The bit timing is repeated for all bits to be transmitted or received. 176/188 310 311 312 t t 314 315 315 1st out bit 2nd out bit t t 317 318 1st in bit 2nd in bit 2) 313 t 316 315 Last out bit t t 317 318 Last in bit ST10F273Z4 ...

Page 177

... The major revision of the device is contained in the device identification register, IDCHIP, located at address F07Ch. For Cxx versions, IDCHIP is set to 1143h. 25.1 Functional limitations The functional limitations identified on the ST10F273Z4 are the following: ● Injected conversion stalling the A/D converter (see stalling the A/D ● ...

Page 178

... A/D converter fills the temporary register again without generating any ADEINT interrupt request and the converter is stalled. The A/D converter stays in the “wait for read ADDAT2 register” condition forever. 178/188 Figure Figure 62 consequence the CPU/PEC ST10F273Z4 61). ...

Page 179

... ST10F273Z4 Figure 61. ADC injection theoretical operation Figure 62. ADC injection actual operation Known limitations ADEINT Interrupt not generated ADDAT2 correctly updated and can be read by software 179/188 ...

Page 180

... CPU interface register (Identifier, DLC, Data, with TxRqst and NewDat [optionally TxIE] bits) and to transfer it into the message object. The new content is then transmitted at the next opportunity, and is not altered by a possibly ongoing transmission of the previous content of the same message object. 180/188 ST10F273Z4 ...

Page 181

... ST10F273Z4 25.1.4 Spurious BREQ pulse in slave mode during external bus arbitration phase Description Sporadic bus errors may occur when the device operates as a slave and the HOLD signal is used for external bus arbitration. After the slave has been granted the bus, it deactivates sporadically BREQ signal for a short time, even though its access to the bus has not been completed ...

Page 182

... TxREL and Tx related timer registers are loaded with the same value as CCy. This is obtained by executing the following instructions: MOV TxREL, #CCy value x =0,1,7,8 MOV Tx, #CCy value x = 0,1,7,8 MOV TxxCON, #data or bfldl/bfldh TxxCON , #mask, #data i.e. an access is made to the T01CON or T78CON register. 182/188 ST10F273Z4 ...

Page 183

... ST10F273Z4 Workarounds The following workarounds make the CAPCOM output toggle as expected: 1) Invert the TxREL and Tx configuration as follow: MOV Tx, #CCy value MOV TxREL, #CCy value bfldl/bfldh TxxCON , #mask, #data or MOV TxxCON, #data 2) Insert a NOP instruction before the T01CON or T78CON configuration: MOV Tx, #value ...

Page 184

... These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: www.st.com. 184/188 ST10F273Z4 ...

Page 185

... ST10F273Z4 Figure 64. PQFP144 - 144-pin plastic Quad Flatpack mm, 0.65 mm pitch, package outline 109 144 Table 84. PQFP144 - 144-pin Plastic Quad Flatpack mm, 0.65 mm pitch, package mechanical data Symbol 31.200 D1 28.000 D3 22.750 e E 31.200 E1 28.000 E3 22.750 ddd 1. Values in inches are converted from mm and rounded decimal places. ...

Page 186

... Min Typ Max 1.60 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27 0.09 0.20 21.80 22.00 22.20 19.80 20.00 20.20 17.50 21.80 22.00 22.20 19.80 20.00 20.20 17.50 0.50 0° 3.5° 7° 0.45 0.60 0.75 1.00 ST10F273Z4 0.08 mm .003 in. b Seating Plane (1) inches Min Typ 0.002 0.053 0.007 0.004 0.858 0.867 0.780 0.787 0.689 0.858 0.867 0.780 0.787 0.689 0.020 0° 3.5° 0.018 0.024 0.039 Max ...

Page 187

... ST10F273Z4 27 Revision history Table 86. Document revision history Date 08-June-2006 10-Jan-2008 Revision 1 Initial release. Replaced ST10F273 by ST10F273Z4. Modified Table 5.: Flash modules sectorization (read operations) on page 26 and Table 6 on page 27 2 Added Section 25: Known Modified Section 26: Package information and modified figures and tables) ...

Page 188

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 188/188 Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST10F273Z4 ...

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