ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet

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ST72651AR6

Manufacturer Part Number
ST72651AR6
Description
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72651AR6

Dual Supply Management
analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying
Flash Card I/O lines (voltage shifting)
5 Usb Endpoints
1 control endpoint
Dtc (data Transfer Coprocessor)
Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

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Device Summary
June 2009
Features
Program memory
User RAM (stack) - bytes
Peripherals
Operating Supply
Package
Operating Temperature
Memories
– Up to 32 KB of High Density Flash (HDFlash)
– For HDFlash devices, In-Application Pro-
– Up to 5 KB of RAM with up to 256 B stack
Clock, Reset and Supply Management
– PLL for generating 48 MHz USB clock using a
– Low Voltage Reset (except on E suffix devic-
– Dual supply management: analog voltage de-
– Programmable Internal Voltage Regulator for
– Clock-out capability
47 programmable I/O lines
– 15 high sink I/Os (8mA@0.6V / 20mA@1.3V)
– 5 true open drain outputs
– 24 lines programmable as interrupt inputs
USB (Universal Serial Bus) Interface
– with DMA for full speed bulk applications com-
– On-Chip 3.3V USB voltage regulator and
– 5 USB endpoints:
– Hardware conversion between USB bulk
Low-power, full-speed USB 8-bit MCU with 32 KB Flash, 5 KB
program memory with read/write protection
gramming (IAP) via USB and In-Circuit pro-
gramming (ICP)
12 MHz crystal
es)
tector on the USB power line to enable smart
power switching from USB power to battery
(on E suffix devices).
Memory cards (2.8V to 3.5V) supplying:
pliant with USB 12 Mbs specification (version
2.0 compliant)
transceivers with software power-down
packets and 512-byte blocks
1 control endpoint
2 IN endpoints supporting interrupt and bulk
2 OUT endpoints supporting interrupt and
bulk
Flash Card I/O lines (voltage shifting)
Up to 50 mA for Flash card supply
RAM, Flash card interface, timer, PWM, ADC,
4.0 to 5.5 V (for USB)
Doc ID 7215 Rev 4
USB, DTC, Timer, ADC, SPI, I
32 Kbytes of Flash program memory
Mass Storage Interface
– DTC (Data Transfer Coprocessor): Universal
2 Timers
– Configurable Watchdog for system reliability
– 16-bit Timer with 2 output compare functions.
2 Communication Interfaces
– SPI synchronous serial interface
– I
D/A and A/D Peripherals
– PWM/BRM Generator (with 2 10-bit PWM/
– 8-bit A/D Converter (ADC) with 8 channels
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
Development Tools
– Full hardware/software development package
LQFP64 (10 x10)
ST72651AR6
Serial/Parallel communications interface, with
software plug-ins for current and future proto-
col standards:
5 Kbyte (256)
BRM outputs)
2
0 to +70 °C
Compact Flash - Multimedia Card -
Secure Digital Card - SmartMediaCard -
Sony Memory Stick - NAND Flash -
ATA Peripherals
C Single Master Interface up to 400 KHz
Dual 3.0 to 5.5 V or 4.0 to 5.5 V (for USB)
2
C, PWM, WDT
LQFP64 10x10
ST72651AR6
I
2
C, SPI
1/161
1

Related parts for ST72651AR6

ST72651AR6 Summary of contents

Page 1

... Full hardware/software development package ST72651AR6 32 Kbytes of Flash program memory 5 Kbyte (256) USB, DTC, Timer, ADC, SPI, I 4.0 to 5.5 V (for USB) LQFP64 (10 x10 +70 °C Doc ID 7215 Rev 4 ST72651AR6 2 I LQFP64 10x10 2 C, PWM, WDT Dual 3 4.0 to 5.5 V (for USB) C, SPI 1/161 ...

Page 2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

... ST72651AR6 1 INTRODUCTION The ST7265x MCU supports volume data ex- change with a host (computer or kiosk) via a full speed USB interface. The MCU is capable of han- dling various transfer protocols, with a particular emphasis on mass storage applications. ST7265x is compliant with the USB Mass Storage Class specifications, and supports related proto- cols such as BOT (Bulk Only Transfer) and CBI (Control, Bulk, Interrupt) ...

Page 5

... The ST72F65x are the Flash versions of the ST7265x in a LQFP64 package. DATA TRANSFER BUFFER 512-byte RAM Buffer BUFFER ACCESS ARBITRATION DATA TRANSFER COPROCESSOR (DTC) LEVEL SHIFTERS DIGITAL AUDIO DEVICE Doc ID 7215 Rev 4 ST72651AR6 2 C Single Master interface (not on all prod- ST7 CORE I2C 5/161 1 ...

Page 6

... ST72651AR6 INTRODUCTION (Cont’d) Figure 3. ST7265x Block Diagram OSCIN 12MHz OSCOUT 48MHz TRANSFER (1280 bytes) USBDP USBDM USBVCC PD[7:0] (8 bits) 16-BIT TIMER* RESET V PP (0.5/5 KBytes) * not available on all products (refer to Table 1: Device Summary) 6/161 1 OSC CLOCK DIVIDER PLL f CPU DATA BUFFER USB ...

Page 7

... DDF V 7 SSF ei0 Doc ID 7215 Rev 4 ST72651AR6 PE2 (HS) / DTC 36 PE1 (HS) / DTC 35 PE0 (HS) / DTC 34 PD7 33 PD6 32 PD5 31 PD4 30 ei1 PD3 29 PD2 28 27 PD1 26 PD0 ...

Page 8

... ST72651AR6 PIN DESCRIPTION (Cont’d) Figure 5. 64-Pin LQFP Package Pinout USBV SS USBDM USBDP USBVCC USBV DD V DDF V SSF DTC / PE5 (HS) DTC / PE6 (HS) DTC / PE7 (HS) DTC / PB0 DTC / PB1 DTC / PB2 DTC / PB3 DTC / PB4 DTC / PB5 8/161 ...

Page 9

... X Port Port Port Port B3 Doc ID 7215 Rev 4 ST72651AR6 “I/O PORTS” on page 45 for more details Main Alternate Function . DTC I/O with serial capability (MMC_CMD) DTC I/O with serial capability (MMC_DAT) DTC I/O with serial capability (MMC_CLK) DTC ...

Page 10

... ST72651AR6 Pin Pin Name 15 PB4/DTC I PB5/DTC I PB6/DTC I PB7/DTC I PA0/DTC I PA1/DTC I PA2/DTC I PA3/DTC I PA4/DTC I PA5/DTC I PA6/DTC I PA7/DTC I PC0/MCO/SS I PC1/DTC/MIS0 I PC2/DTC/MOSI I PC3/DTC/SCK I DD1 SS1 33 PC4/DTC ...

Page 11

... Main Power supply voltage (3V - 5.5V on devices without LVD, otherwise 4V - 5.5V). Analog supply voltage Analog ground Digital ground Input/Output Oscillator pins. These pins connect a 12 MHz parallel-resonant crystal external source to the on-chip oscillator. Doc ID 7215 Rev 4 ST72651AR6 Main Alternate Function 1) / Analog Input 5 DTC 1) / ...

Page 12

... ST72651AR6 Figure 6. Multimedia Card Or Secure Digital Card Writer Application Example 100nF 4.7μF USBV DD =4.0-5.5V USBVDD USB Port 1.5KΩ USB 5V VCC 100nF USB GND GND MultiMedia Card Pin ST72F65 pin (1) ST7 / DTC (1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. ...

Page 13

... I/O by configuring it as such by the op- tion byte. Doc ID 7215 Rev 4 DD (4) I/O LOGIC FLASH (2) RE R/B WP CE1 PA3 PA4 PA7 DTC DTC ST7 ST72651AR6 LED1 LED2 12V for VPP Flash prog. (connect to GND if not used) (2) (2)(3) CE2 PE1 PE0 ST7 ST7 13/161 1 ...

Page 14

... ST72651AR6 Figure 8. Compact Flash Card Writer Application Example 100nF 4.7μF USBV DD =4.0-5.5V USBVDD USB Port 1.5KΩ USB 5V VCC 100nF USB USB GND GND 1 level translator Table 3. Compact Flash Card Writer Pin Assignment VS1, VS2, WAIT, Compact Flash D0-7 D8-15 CS1, INPACK, Card Pin ...

Page 15

... MEMORY STICK CMD PE5 DTC used as a normal I/O by configuring it as such by the op- tion byte. Doc ID 7215 Rev I/O LOGIC FLASH V DDF 100nF DAT PE6 DTC ST72651AR6 LED1 LED2 12V for VPP Flash prog. (connect to GND if not used) CLK PE7 DTC 15/161 1 ...

Page 16

... ST72651AR6 3 REGISTER & MEMORY MAP As shown in Figure 10, the MCU is capable of ad- dressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 80 bytes of register locations Kbytes of RAM and Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh ...

Page 17

... ADC Control Status Register Watchdog Control Register Reserved Area (3 bytes) Power Control Register SPI Data I/O Register SPI Control Register SPI Control/Status Register DTC Control Register DTC Status Register DTC Pointer Register Doc ID 7215 Rev 4 ST72651AR6 Reset Status Remarks 00h R/W 00h R/W 00h R/W 00h R/W ...

Page 18

... ST72651AR6 Address Block Register Label 0020h TCR1 0021h TCR2 0022h TSR 0023h CHR 0024h CLR 0025h TIM ACHR 0026h ACLR 0027h OC1HR 0028h OC1LR 0029h OC2HR 002Ah OC2LR 002Bh Flash 002Ch ITSPR0 002Dh ITSPR1 ITC 002Eh ITSPR2 002Fh ITSPR3 0030h USBISTR ...

Page 19

... Register Label 004Ch MISCR3 004Dh PWM0 1) 004Eh PWM BRM10 004Fh PWM1 Note 1. If the peripheral is present on the device (see Device Summary on page 1) Register name Miscellaneous Register 3 10-bit PWM/BRM registers Doc ID 7215 Rev 4 ST72651AR6 Reset Status Remarks 00h R/W 80h R/W 00h R/W 80h R/W 19/161 1 ...

Page 20

... ST72651AR6 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis using an external V supply. PP The HDFlash devices can be programmed and ...

Page 21

... CIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case. Doc ID 7215 Rev 4 ST72651AR6 : programming voltage PP APPLICATION BOARD ICC CONNECTOR HE10 CONNECTOR TYPE ...

Page 22

... ST72651AR6 FLASH PROGRAM MEMORY (Cont’d) 4.6 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading) ...

Page 23

... Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 0 ACCUMULATOR 0 X INDEX REGISTER 0 Y INDEX REGISTER PCL 0 PROGRAM COUNTER 0 C CONDITION CODE REGISTER X 0 STACK POINTER Doc ID 7215 Rev 4 ST72651AR6 Figure 13 are not X = Undefined Value 23/161 1 ...

Page 24

... ST72651AR6 CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions ...

Page 25

... A subroutine call occupies two locations and an in- terrupt five locations in the stack area. PUSH PCH PCL PCH PCL Doc ID 7215 Rev 4 ST72651AR6 Figure 14. POP Y IRET PCH SP PCL PCH PCH SP PCL PCL RET or RSP ...

Page 26

... ST72651AR6 6 SUPPLY, RESET AND CLOCK MANAGEMENT 6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a 12 MHz crystal or an external clock signal to drive the internal oscillator. The internal clock ( derived from the inter- CPU nal oscillator frequency (f ), which is 12 Mhz in OSC Stand-alone mode and 48Mhz in USB mode ...

Page 27

... SHORT EXT. RESET RUN RUN ACTIVE PHASE t t w(RSTL)out w(RSTL)out t t h(RSTL)in h(RSTL)in DELAY Doc ID 7215 Rev 4 ST72651AR6 Figure 17: Figure 19 LONG EXT. WATCHDOG RESET RESET RUN ACTIVE ACTIVE PHASE PHASE t w(RSTL)out WATCHDOG UNDERFLOW INTERNAL RESET (min 512 T VECTOR FETCH ...

Page 28

... ST72651AR6 RESET SEQUENCE MANAGER (Cont’d) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details ...

Page 29

... In USB mode the delay is 256 clock cycles count- ed from when the PLL LOCK signal goes high. The RESET vector fetch phase duration is 2 clock cycles. 512 x t CPU(STAND-ALONE) PLL Startup time (undefined) 400 µs typ. Doc ID 7215 Rev 4 ST72651AR6 FETCH VECTOR FETCH VECTOR 256 x t CPU(USB) Section 6.4. 29/161 1 ...

Page 30

... ST72651AR6 6.3 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below a V DDA value. This means that it secures the power-up as well as the power-down, keeping the ST7 in reset. ...

Page 31

... USBEN is set to output low level by hardware. This signal can be used to control an external transistor (USB SWITCH) to change the power supply configuration (see – The microcontroller can be USB bus powered Doc ID 7215 Rev 4 ST72651AR6 pin) DD pin. In this mode: DD pin is supplied by a 4.0 to 5.5V supply ...

Page 32

... ST72651AR6 POWER SUPPLY MANAGEMENT (Cont’d) 6.4.2.1 Switching from Stand-Alone Mode to USB Mode In Stand-Alone Mode, when the user plugs in the USB cable, 4V min. is input to USBV chip power Supply Manager generates an internal interrupt when USBV reaches USBV DD PLGIE bit in the PCR register is set). The user pro- gram then can finish the current processing, and MUST generate a software RESET afterwards ...

Page 33

... Caution: In order to avoid applying excessive volt- age to the Storage Media, a minimum delay must be ensured during (and after if needed) the reset phase, prior to switching ON the external STOR- . Fail- PLLmin AGE switch. Doc ID 7215 Rev 4 ST72651AR6 is disconnected from DD Figure 24. voltage (higher than step-up converter voltage decreases dur- DD ...

Page 34

... ST72651AR6 POWER SUPPLY MANAGEMENT (Cont’d) Figure 24. Power Supply Management: Dual Power Supply STAND-ALONE USBV SUPPLY SUPPLY VOLTAGES PLG INTERRUPT REQUEST RESET S/W STAND-ALONE RESET STATUS PROCESSING USBEN HI-Z V IT+(LVD) STAND-ALONE V pin DD voltage PLL PLL OFF ON/OFF 48 MHz NO CLOCK SIGNAL CLOCK CRYSTAL (12MHz) SOURCE 1 ...

Page 35

... PCR register). -driven I/Os cannot Section Caution: The user should ensure that V not exceed the maximum rating specified for the Storage Media V AGE switch on. Doc ID 7215 Rev 4 ST72651AR6 and USBV pins are supplied with the current DDF max when switching STOR- ...

Page 36

... ST72651AR6 POWER SUPPLY MANAGEMENT (Cont’d) 6.4.4 Register Description POWER CONTROL REGISTER (PCR) Reset Value: 0000 0000 (00h) 7 ITM PLG VSE ITPF PLG Bit 7 = ITPF Voltage Input Threshold Plus Flag This bit is set by hardware when USBV over USBV and cleared by hardware when US- ...

Page 37

... Doc ID 7215 Rev 4 Level Low High TLI Interrupt has the same or a lower software priority than current one I1:0 THE INTERRUPT STAYS PENDING STACK PC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR ST72651AR6 37/161 ...

Page 38

... ST72651AR6 INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first ...

Page 39

... Warning: A stack overflow may occur without no- tifying the software of the failure. TLI IT0 IT1 IT1 IT3 TLI IT0 IT1 IT3 IT4 IT4 Doc ID 7215 Rev 4 ST72651AR6 Figure 27 and Figure 28 SOFTWARE I1 PRIORITY LEVEL ...

Page 40

... ST72651AR6 INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ware priority. Interrupt Software Priority Level Level 0 (main) ...

Page 41

... External Interrupt Port C 10 SPI SPI interrupt Function/Example Pop CC I1:0=11 ? I1:0<>11 ? Mem => CC Load Load Software NMI Register Description Label DTCSR USBISTR USBISTR I2CSRx SPICSR Doc ID 7215 Rev 4 ST72651AR6 ...

Page 42

... ST72651AR6 INTERRUPTS (Cont’d) Table 11. Nested Interrupts Register Map and Reset Values Address Register 7 Label (Hex.) 002Ch I1_3 ISPR0 Reset Value 1 002Dh I1_7 ISPR1 Reset Value 1 002Eh I1_11 ISPR2 1 Reset Value 002Fh ISPR3 Reset Value 1 42/161 DTC EI0 I0_3 ...

Page 43

... Figure 29. WAIT Mode Flow Chart ). CPU N INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack. The set during the interrupt routine and cleared when the CC register is popped. Doc ID 7215 Rev 4 ST72651AR6 WFI INSTRUCTION OSCILLATOR ON PERIPH. CLOCK ON CPU CLOCK OFF I1:0] BITS CLEARED ...

Page 44

... ST72651AR6 POWER SAVING MODES (Cont’d) 8.3 HALT MODE The HALT mode is the MCU lowest power con- sumption mode. The HALT mode is entered by ex- ecuting the HALT instruction. The internal oscilla- tor is then turned off, causing all internal process- ing to be stopped, including the operation of the on-chip peripherals ...

Page 45

... The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. Doc ID 7215 Rev 4 ST72651AR6 Figure 32). 45/161 1 ...

Page 46

... ST72651AR6 I/O PORTS (Cont’d) 9.2.2 Output Modes Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status: DR Push-pull The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch ...

Page 47

... FROM OTHER BITS Pull-Up Off On Off NI is not implemented in the true open drain pads. A local protection between Doc ID 7215 Rev 4 ST72651AR6 P-BUFFER DDF (see table below) PULL-UP (see table below DDF PULL-UP ...

Page 48

... ST72651AR6 I/O PORTS (Cont’d) Table 13. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status ...

Page 49

... Section ed by option byte 15.1) see Section floating open drain floating open drain floating True open drain floating floating True open drain Doc ID 7215 Rev 4 ST72651AR6 Figure 32 Other transitions 00 10 INPUT OUTPUT OUTPUT floating open-drain push-pull (reset state DDR, OR Output ...

Page 50

... ST72651AR6 I/O PORTS (Cont’d) 9.4 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bits 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken into account even if the pin is configured as an input ...

Page 51

... PFDR MSB 0010h PFDDR Related Documentation AN970: SPI Communication between ST7 and EEPROM Unused AN1045: S/W implementation of I2C bus master AN1048: Software LCD driver Doc ID 7215 Rev 4 ST72651AR6 LSB LSB LSB LSB LSB LSB 51/161 ...

Page 52

... ST72651AR6 10 MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity Interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei0 interrupts (Port A): IS11 IS10 External Interrupt Sensitivity 0 0 Falling edge & low level ...

Page 53

... PWM0 Output alternate function enabled IS10 MCO IS21 Doc ID 7215 Rev 4 ST72651AR6 External Interrupt Sensitivity 0 Falling edge & low level 1 Rising edge only 0 Falling edge only 1 Rising and falling edge IS20 CP1 CP0 ...

Page 54

... ST72651AR6 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’ ...

Page 55

... CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids en- tering other peripheral interrupt routines after ex- ecuting the external interrupt routine corresponding to the wake-up event (reset or ex- ternal interrupt). Doc ID 7215 Rev 4 ST72651AR6 55/161 1 ...

Page 56

... ST72651AR6 WATCHDOG TIMER (Cont’d) 11.1.8 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by Table 18. Watchdog Timer Register Map and Reset Values Address Register 7 Label (Hex.) ...

Page 57

... The protocol used to read or write from the I/O port is defined by the S/W plug-in in the DTC RAM. ST7 DATA/ADDRESS BUS LSB DATA TRANSFER COPROCESSOR DTC RAM LOAD INIT RUN DTCSR Doc ID 7215 Rev 4 ST72651AR6 Figure DATA TO USB TRANSFER INTERFACE BUFFER ERRORSTOP INTERRUPT REQUEST 34. The 57/161 1 ...

Page 58

... ST72651AR6 Data Transfer Coprocessor (Cont’d) When the USB interface is used, data transfer is typically controlled by a host computer. The ST7 core can also read from and write to the data buffer of the DTC. Typically, the ST7 controls the application when the USB not used (autono- mous mode) ...

Page 59

... This register is written by software. It gives the ad- dress of an entry point in the protocol software that has previously been loaded in the DTC RAM. Note: To start executing the function, after writing this address, set the INIT bit. Doc ID 7215 Rev 4 ST72651AR6 ERROR ...

Page 60

... ST72651AR6 11.2.8.1 Data Transfer Coprocessor (Cont’d) Table 19. DTC Register Map and Reset Values Address Register Label (Hex.) 1C DTCCR 1D DTCSR MSB 1F DTCPR 60/161 ERREN Doc ID 7215 Rev STOPEN LOAD INIT ...

Page 61

... Interrupts By reading the Interrupt Status register, applica- tion software can know which USB event has oc- curred. 48 MHz ENDPOINT REGISTERS BUFFER SIE INTERFACE USB REGISTERS Doc ID 7215 Rev 4 ST72651AR6 CPU Address, data busses and interrupts USB DATA BUFFER 61/161 1 ...

Page 62

... ST72651AR6 USB INTERFACE (Cont’d) USB Endpoint RAM Buffers There are five bidirectional Endpoints including one control Endpoint 0. Endpoint 1 and Endpoint 2 are counted as 4 bulk or interrupt Endpoints (two IN and two OUT). Endpoint 0 and Endpoint 1 are both bytes in size. Endpoint bytes in size and can be ...

Page 63

... Endpoint 0 Buffer IN Endpoint 1 Buffer OUT Endpoint 1 Buffer IN 158Fh Endpoint 2 Buffer OUT Endpoint 2 Buffer IN 1590h USB DATA 15CFh 1650h USB DATA USB DATA USB DATA USB DATA 1A4Fh Doc ID 7215 Rev 4 ST72651AR6 64-byte buffer 512-byte buffer as 64-byte slices 512-byte buffer as 64-byte slices 63/161 1 ...

Page 64

... ST72651AR6 USB INTERFACE (Cont’d) 11.3.4 USB Data Buffer Manager The USB Data Buffer Manager performs the data transfer between the USB interface and the two 512 Bytes RAM areas used for Endpoint 2 in both Upload and Download modes. It also controls the ...

Page 65

... B1 B0 USB DATA BUFFER MANAGER BUFFER ACCESS ARBITRATION DATA TRANSFER COPROCESSOR (DTC) DTC I/Os (EXTERNAL DEVICES) Doc ID 7215 Rev 4 ST72651AR6 DATA TRANSFER BUFFER (1280 bytes) 1550h USB EP0 USB EP1 USB EP2 Parameters 1650h 512-byte RAM Buffer 1850h 512-byte RAM Buffer 1A4Fh ...

Page 66

... ST72651AR6 USB INTERFACE (Cont’d) 11.3.5 Low Power modes Mode No effect on USB. WAIT USB interrupt events cause the device to exit from WAIT mode. USB registers are frozen. In halt mode, the USB is inactive. USB operations resume when the MCU is woken interrupt with HALT “ ...

Page 67

... No SETUP overrun detected 1: SETUP overrun detected When this event occurs, the USBSR register is not updated because the only source of the SOVR event is the SETUP token reception on the Control Endpoint (EP0). Doc ID 7215 Rev 4 ST72651AR6 0 SOVR ERROR SUSP ESUSP RESET SOF 0 67/161 1 ...

Page 68

... ST72651AR6 USB INTERFACE (Cont’d) Bit 4 = ERR Error. This bit is set by hardware whenever one of the er- rors listed below has occurred error detected 1: Timeout, CRC, bit stuffing, nonstandard framing or buffer overrun error detected Note: Refer to the ERR[2:0] bits in the USBSR register to determine the error type. ...

Page 69

... This bit is set by hardware when a CTR interrupt 0 occurs on Endpoint 1 or Endpoint 2. 0: OUT transaction 1: IN transaction Bits 4:3 = EP[1:0] Endpoint number. These bits identify the endpoint which required at- tention Endpoint Endpoint Endpoint 2 Doc ID 7215 Rev 4 ST72651AR6 0 EP1 EP0 ERR2 ERR1 ERR0 PID Name 0 OUT SETUP ...

Page 70

... ST72651AR6 USB INTERFACE (Cont’d) Bits 2:0 = ERR[2:0] Error type. These bits identify the type of error which oc- curred: ERR2 ERR1 ERR0 Meaning error Bitstuffing error CRC error EOP error (unexpected end packet or SE0 not followed by J-state) ...

Page 71

... STAT_ STAT_ DTOG the received data before acknowledging a new _RX RX1 RX0 transaction. Doc ID 7215 Rev 4 ST72651AR6 Meaning DISABLED: reception trans- 0 fers cannot be executed. STALL: the endpoint is stalled 1 and all reception requests re- sult in a STALL handshake. NAK: the endpoint is naked ...

Page 72

... ST72651AR6 USB INTERFACE (Cont’d) ENDPOINT 1 TRANSMISSION (EP1TXR) Read/Write Reset value: 0000 0000 (00h) 7 CTR_T This register is used for controlling Endpoint 1 transmission. Bits 2:0 are also reset by a USB re- set, either received from the USB or forced through the FRES bit in the CTLR register. ...

Page 73

... This bit must be cleared after the corresponding interrupt has been serviced CTR in transmission on Endpoint 2 1: Correct transfer in transmission on Endpoint 2 Doc ID 7215 Rev 4 ST72651AR6 Meaning DISABLED: reception trans- fers cannot be executed. STALL: the endpoint is stalled and all reception requests re- sult in a STALL handshake ...

Page 74

... ST72651AR6 USB INTERFACE (Cont’d) Bit 2= DTOG_TX Data Toggle, for transmission transfers. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX and DTOG_RX are normally updated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token ...

Page 75

... CNT4 MOD0 CNT6 CNT5 CNT4 CNT6 CNT5 CNT4 Doc ID 7215 Rev 4 ST72651AR6 BUFNUM BUF1ST BUF0ST SUSP ESUSP RESET SUSPM ESUSPM RESETM RESUME PDWN FSUSP ADD3 ADD2 ADD1 ...

Page 76

... ST72651AR6 11.4 16-BIT TIMER 11.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. 11.4.2 Main Features Programmable prescaler: f ■ CPU Overflow status flag and maskable interrupt ■ Output compare functions with ■ – 2 dedicated 16-bit registers – 2 dedicated programmable signals – ...

Page 77

... REGISTER REGISTER 1 16 TIMER INTERNAL BUS 16 16 OUTPUT COMPARE CIRCUIT OCF2 (Status Register) SR FOLV1 OLVL2 0 OLVL1 OC1E (Control Register 1) CR1 Doc ID 7215 Rev 4 ST72651AR6 LATCH1 LATCH2 0 0 CC1 CC0 0 OC2E (Control Register 2) CR2 OCMP1 pin OCMP2 pin 0 77/161 1 ...

Page 78

... ST72651AR6 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +Δt LS Byte value Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically ...

Page 79

... TIMER OVERFLOW FLAG (TOF) Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. FFFD FFFE FFFF 0000 0001 0002 0003 FFFC FFFD FFFC FFFD Doc ID 7215 Rev 4 ST72651AR6 0000 0001 0000 79/161 1 ...

Page 80

... ST72651AR6 16-BIT TIMER (Cont’d) 11.4.3.2 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- ...

Page 81

... Figure CPU CPU 82). R register and the i OC1E CC1 OC2E (Control Register 2) CR2 (Control Register 1) CR1 OCIE FOLV2 FOLV1 OCF1 OCF2 Doc ID 7215 Rev 4 CC0 Latch OLVL2 OLVL1 1 Latch (Status Register) SR ST72651AR6 OCMP1 Pin OCMP2 Pin 81/161 1 ...

Page 82

... ST72651AR6 16-BIT TIMER (Cont’d) Figure 46. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 47. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH ...

Page 83

... These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask bits in the CC register are reset (RIM instruction). Description Event Flag OCF1 OCF2 TOF Doc ID 7215 Rev 4 ST72651AR6 Enable Exit Exit Control from from Bit Wait Halt ...

Page 84

... ST72651AR6 16-BIT TIMER (Cont’d) 11.4.6 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (TCR1) ...

Page 85

... The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read CC0 or write the low byte of the OC2R (OC2LR) reg- 0 ister Bits 2:0 = Reserved, forced by hardware Doc ID 7215 Rev 4 ST72651AR6 TOF 0 OCF2 0 0 85/161 0 0 ...

Page 86

... ST72651AR6 16-BIT TIMER (Cont’d) OUTPUT COMPARE 1 (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 1 (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...

Page 87

... CC1 CC0 OCF2 ST72651AR6 OLVL1 LSB 1 1 LSB 0 0 LSB 1 1 LSB 0 0 LSB 0 0 LSB 0 0 LSB 0 0 LSB ...

Page 88

... ST72651AR6 11.5 PWM/BRM GENERATOR (DAC) 11.5.1 Introduction This PWM/BRM peripheral includes a 6-bit Pulse Width Modulator (PWM) and a 4-bit Binary Rate Multiplier (BRM) Generator. It allows the digital to analog conversion (DAC) when used with external filtering. Note: The number of PWM and BRM channels available depends on the device. Refer to the de- vice pin description and register map ...

Page 89

... VOLTAGE DD PWM Duty Cycle 50% R ext C R=R ext ext Note: after a reset these pins are tied low by de- fault and are not in a high impedance state. "DISCHARGE" "CHARGE" "CHARGE" Doc ID 7215 Rev 4 ST72651AR6 V RIPPLE (mV) 0.128 78 1.28 7.8 12.8 0.78 V ripple (mV) "DISCHARGE" V ripple "DISCHARGE" V OUTAVG (mV) ...

Page 90

... ST72651AR6 PWM/BRM GENERATOR (Cont’d) BRM Generation The BRM bits allow the addition of a pulse to wid standard PWM pulse for specific PWM cy- cles. This has the effect of “fine-tuning” the PWM Duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps ...

Page 91

... Figure 53. Graphical Representation of 4-Bit BRM Added Pulse Positions BRM VALUE 0001 bit0=1 0010 bit1=1 0100 bit2=1 1000 bit3=1 Examples 0110 1111 = T CPU BRM EXTENDED PULSE PWM Pulse Number (0-15 Doc ID 7215 Rev 4 ST72651AR6 = BRM = 1 BRM = 91/161 ...

Page 92

... ST72651AR6 PWM/BRM GENERATOR (Cont’d) Figure 54. Precision for PWM/BRM Tuning for VOUTEFF (After filtering) 11.5.4 Register Description On a channel basis, the 10 bits are separated into two data registers: Note: The number of PWM and BRM channels available depends on the device. Refer to the de- vice pin description and register map ...

Page 93

... Reset Value 1 BRM10 B7 4E Reset Value 0 PWM1 1 4F Reset Value POL POL Doc ID 7215 Rev 4 ST72651AR6 93/161 ...

Page 94

... ST72651AR6 11.6 SERIAL PERIPHERAL INTERFACE (SPI) 11.6.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multimaster sys- tem ...

Page 95

... Four possible data/clock timing relationships may be chosen (see must be programmed with the same timing mode. LSBit MISO MISO MOSI MOSI SCK SCK SS V DDF Doc ID 7215 Rev 4 ST72651AR6 Figure 59) but master and slave SLAVE MSBit 8-BIT SHIFT REGISTER SS Not used managed by software LSBit 95/161 ...

Page 96

... ST72651AR6 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR regis- ter (see Figure 58) ...

Page 97

... SPIDR register are inhibited until the SPICSR reg- ister is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section Doc ID 7215 Rev 4 ST72651AR6 Section 57. If CPHA=1 SS must 11.6.5.2). 97/161 ...

Page 98

... ST72651AR6 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 59). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0) ...

Page 99

... WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see SPIF =0 WCOL=0 Read SPICSR RESULT Read SPIDR WCOL=0 Doc ID 7215 Rev 4 ST72651AR6 Section 11.6.3.2 Slave Select Figure 60). Note: Writing to the SPIDR regis- ter instead of reading it does not reset the WCOL bit 99/161 ...

Page 100

... ST72651AR6 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.5.4 Single Master System A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 61). The master device selects the individual slave de- vices by using four pins of a parallel port to control the four SS pins of the slave devices. ...

Page 101

... Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Doc ID 7215 Rev 4 ST72651AR6 Section Enable Exit Exit Event ...

Page 102

... ST72651AR6 SERIAL PERIPHERAL INTERFACE (Cont’d) 11.6.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever ...

Page 103

... Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value lo- cated in the buffer and not the content of the shift register (see Doc ID 7215 Rev 4 ST72651AR6 Management Figure 55) ...

Page 104

... ST72651AR6 SERIAL PERIPHERAL INTERFACE (Cont’d) Table 33. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 19 Reset Value SPICR SPIE 1A Reset Value SPICSR SPIF 1B Reset Value 104/161 SPE SPR2 MSTR WCOL OVR MODF Doc ID 7215 Rev 4 ...

Page 105

... A 9th clock pulse follows the 8 clock cycles byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer bus ure 62. MSB 1 2 Doc ID 7215 Rev 4 ST72651AR6 2 C bus. This selection is made by soft- ACK 8 9 STOP CONDITION Fig- VR02119B 105/161 ...

Page 106

... ST72651AR6 I²C SINGLE MASTER BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. 2 The speed of the I C interface may be selected between Standard (up to 100KHz) and Fast I (up to 400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the micro- controller to write the byte in the Data Register ...

Page 107

... SDA line can remain low if the last bits transmitted are all 0. While AF=1, the SCL line may be held low due BTF flags that are set at the same time then necessary to release both lines by software. Doc ID 7215 Rev 4 ST72651AR6 Figure 64 Transfer se- Figure 64 Transfer sequencing 107/161 ...

Page 108

... ST72651AR6 I²C SINGLE MASTER BUS INTERFACE (Cont’d) Figure 64. Transfer Sequencing Master receiver: S Address A EV1 EV2 Master transmitter: S Address A EV1 EV2 EV4 Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV2: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). ...

Page 109

... They generate an interrupt if the corresponding Enable Control Bit is set and the I-bits in the CC register are reset (RIM instruction). Description C interface is inactive and does not acknowledge data on the bus. The I ITE Doc ID 7215 Rev 4 ST72651AR6 2 C interface INTERRUPT EVF Enable Exit Exit ...

Page 110

... ST72651AR6 I²C SINGLE MASTER BUS INTERFACE (Cont’d) 11.7.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h START ACK Bit 7:6 = Reserved. Forced hardware. Bit Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled ...

Page 111

... START=1). An interrupt is generated if ITE= cleared by software reading SR1 register followed by writing the address byte in DR register also cleared by hardware when the interface is disa- bled (PE=0 Start condition 1: Start condition generated Doc ID 7215 Rev 4 ST72651AR6 Figure 64). BTF is is generated (following a write ...

Page 112

... ST72651AR6 I²C SINGLE MASTER BUS INTERFACE (Cont’ STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h Bit 7:5 = Reserved. Forced hardware. Bit Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE= cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0) ...

Page 113

... Address Register 7 Name (Hex.) CCR FM/SM 43 Reset Value 0 DR DR7 46 Reset Value CC6 CC5 CC4 DR6 DR5 DR4 Doc ID 7215 Rev 4 ST72651AR6 CC3 CC2 CC1 DR3 DR2 DR1 CC0 0 DR0 0 113/161 ...

Page 114

... ST72651AR6 11.8 8-BIT A/D CONVERTER (ADC) 11.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources ...

Page 115

... Note: The A/D converter may be disabled by reset- ting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.8.5 Interrupts None Doc ID 7215 Rev 4 ST72651AR6 ADCCSR READ t CONV OPERATION t LOAD COCO BIT SET ...

Page 116

... ST72651AR6 8-BIT A/D CONVERTER (ADC) (Cont’d) 11.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by hardware when a conversion is complete cleared by software when reading the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved ...

Page 117

... Table 35. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0012h Reset Value 0 ADCCSR COCO 0013h Reset Value ADON CH3 Doc ID 7215 Rev 4 ST72651AR6 CH2 CH1 CH0 117/161 ...

Page 118

... ST72651AR6 12 INSTRUCTION SET 12.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset The CPU Instruction set is designed to minimize the number of bytes required per instruction Table 36 ...

Page 119

... The pointer address is a byte, the pointer size is a byte, thus allowing addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Doc ID 7215 Rev 4 ST72651AR6 119/161 ...

Page 120

... ST72651AR6 INSTRUCTION SET OVERVIEW (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register value ( with a pointer value located in memory. The point- er address follows the opcode ...

Page 121

... It also changes an instruction using X indexed ad- dressing mode to an instruction using indirect X in- dexed addressing mode. PIY 91 direct indexed addressing mode one. Doc ID 7215 Rev 4 ST72651AR6 NEG MUL RRC SWAP SLA CALL CALLR ...

Page 122

... ST72651AR6 INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call subroutine CALLR Call subroutine relative ...

Page 123

... I1 (level 3) C <= A <= 0 reg <= A <= 0 reg => A => C reg => A => C reg A7-A4 <=> A3-A0 reg, M tnz lbl1 S/W interrupt XOR M A Doc ID 7215 Rev 4 ST72651AR6 Src reg ...

Page 124

... ST72651AR6 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the ...

Page 125

... Ratings section 14.2 on page 152 or V could damage the device if an unintentional internal reset DD SS maximum is respected INJ(PIN) < lines must always be connected to the external supply. Doc ID 7215 Rev 4 ST72651AR6 Maximum value 6 2000 Maximum value 3) 100 ± ...

Page 126

... ST72651AR6 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions Symbol Parameter Supply voltage with USB peripheral ena- bled V DD Supply voltage with USB peripheral disa- bled and LVD off Analog voltage supply V DDA V Analog ground SSA f External clock frequency OSC T Ambient temperature range A Figure 70. f ...

Page 127

... T . Not tested on LVD devices (without E suf- DD OSC A Conditions USBV -USBV IT+ IT- and USBV . Refer to Section 6.4.2.1 DDF and OSC A Conditions USB Mode: VSET[1:0]=11 Doc ID 7215 Rev 4 ST72651AR6 Min Typ Max Unit 2.9 3.5 3.8 2.6 3.1 3.5 150 300 10 MHz. 0.3 10 Min Typ Max Unit 3.50 3.80 4.00 3.30 3 ...

Page 128

... ST72651AR6 13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- vice consumption, the two current values must be 13.4.1 RUN Mode ...

Page 129

... CPU CPU 8 MHz 6 MHz 3 MHz ≤5.5V range) and V =5V (4V≤ (no load), all peripherals in reset state; clock input (OSC1 Doc ID 7215 Rev 4 ST72651AR6 1) Typ Max 8 3 ≤4.0V range). =3.3V (3V≤ 5.5V and f = 8MHz. CPU 2) Unit 129/161 ...

Page 130

... ST72651AR6 SUPPLY CURRENT CHARACTERISTICS (Cont’d) 13.4.3 HALT Mode Symbol Parameter I Supply current in HALT mode HALT Notes: 1. All I/O pins in input mode with a static value USB Transceiver, USB voltage detector and ADC are powered down. 3. Based on characterization, not tested on production. 13.4.4 SUSPEND Mode ...

Page 131

... Conditions f =8MHz CPU 1) f =8MHz CPU Conditions 2) 2) ≤V ≤ 90% 10 f(OSC1) w(OSC1H) OSC2 Not connected internally OSC1 Doc ID 7215 Rev 4 ST72651AR6 . Min Typ Max 250 500 1500 10 22 1.25 2.75 Min Typ Max 0.7xV 0.3xV ±1 ...

Page 132

... ST72651AR6 13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for V 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Memory Operating Conditions MHz. CPU DUAL VOLTAGE FLASH MEMORY Symbol Parameter f Operating Frequency CPU V Programming Voltage Current Internal V Stabilization Time ...

Page 133

... OSC conforms to IEC 1000-4-2 =5V, T =+25°C, f =12MHz OSC conforms to IEC 1000-4-4 Max vs. Monitored [f OSC Frequency Band 12/6MHz 0.1MHz to 30MHz 30MHz to 130MHz 130MHz to 1GHz SAE EMI Level ST72651AR6 Level/ Class 3B 4A Unit /f ] CPU 22 27 dBμ 133/161 ...

Page 134

... ST72651AR6 EMC CHARACTERISTICS (Cont’d) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the application note AN1181. Absolute Maximum Ratings ...

Page 135

... = =50pF L 5) Between 10% and 90% 6) Figure ). Data based on design simulation and/or technology ST72XXX UNUSED I/O PORT Doc ID 7215 Rev 4 ST72651AR6 unless otherwise specified. A Min Typ Max V 0.3xV ss 0.7xV V DD 400 200 70 100 130 130 200 260 5 25 ...

Page 136

... ST72651AR6 . I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 76. V and V vs 3.5 3 2.5 2 1.5 1 0.5 0 2.5 3 Figure 77. Typical I vs -10 -20 -30 -40 -50 -60 -70 -80 - Vdd (V) 136/161 with 3.5 4 Vdd (V) with V =V Figure 78. Typical 300 250 200 150 100 ...

Page 137

... OSC 82) 83) 84) =5V (standard) Figure 81. Typical V 0.8 0.7 0.6 0.5 0.4 0.3 0 VSS . True open drain I/O pins does not have V VDD Doc ID 7215 Rev 4 ST72651AR6 unless otherwise specified. A Conditions Min Max I =+5mA 1 =+2mA 0 =+20mA 1 =+8mA 0 =-5mA V -1 =-2mA V -0 ...

Page 138

... ST72651AR6 I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 82.Typical V vs 0.35 0.3 0.25 0.2 0.15 0.1 0. Vdd (V) Figure 83. Typical V vs 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0. Vdd (V) Figure 84. Typical V vs 0.7 0.6 0.5 0.4 0.3 0.2 0 Vdd (V) 138/161 (standard I/Os (high-sink I/Os) DD 1.6 1.4 1.2 1 0.8 0.6 0.4 0 2.5 2 1 Doc ID 7215 Rev ...

Page 139

... V = =+2mA =3.3V DD External pin or internal reset sources 5) . VSS can be ignored. h(RSTL)in Doc ID 7215 Rev 4 ST72651AR6 unless otherwise specified. A Min Typ Max V 0.3xV SS 0.7xV DD 400 0.68 0.95 0.28 0.45 70 100 130 200 4 20 Section 13.2 and the sum of I Unit ...

Page 140

... ST72651AR6 Figure 85. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF Figure 86. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01μF Required Note 1: – The reset network protects the device against parasitic resets. – The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). – ...

Page 141

... When the ICP mode is not required by the application and T unless otherwise specified. DD OSC A Conditions Pin PP PROGRAMMING TOOL pin must be tied Doc ID 7215 Rev 4 ST72651AR6 Min Max Unit V 0 -0.1 12.6 DD μA ± 10kΩ ST72XXX . SS 141/161 ...

Page 142

... ST72651AR6 13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 13.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 13.10.2 PWM Generator Symbol Parameter T Repetition rate Res Resolution s Output step 142/161 , Refer to I/O port characteristics for more details on DD ...

Page 143

... Slave (after enable edge) Master (after enable edge c(SCK) t w(SCKH w(SCKL) v(SO) MSB OUT BIT6 OUT t h(SI) MSB IN BIT1 IN and 0.7xV . DD DD Doc ID 7215 Rev 4 ST72651AR6 Min Max f /128 f /4 CPU CPU f =8MHz 0.0625 2 CPU f /2 CPU 0 f =8MHz 4 CPU see I/O port pin description ...

Page 144

... ST72651AR6 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 89. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 90. SPI Master Timing Diagram SS INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 ...

Page 145

... C Bus and Timing Diagram V DD 100Ω SDAI 100Ω SCLI ST72XXX t t su(SDA) h(SDA r(SCK) f(SCK) and 0.7xV . DD DD Doc ID 7215 Rev 4 ST72651AR6 2 C interface meets the 2 C communication Fast mode Max Min Max 1.3 0.6 100 2) 3) ...

Page 146

... ST72651AR6 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 2 13.11 Inter IC Control Interface Parameter Bus free time between a STOP and START con- dition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock ...

Page 147

... VSE VOL RL of 1.5K ohms to 3.6V VOH RL of 15K ohm =4.0V - 5.5V DD USBV I Max = 3mA LOAD Crossover points tr USB: Full speed electrical characteristics Symbol Conditions tr Note 1,CL= Note 1, CL=50 pF trfm tr/tf VCRS Doc ID 7215 Rev 4 ST72651AR6 2) Min. Max. 0.2 0.8 2.5 1.3 2.0 1) 0.3 1) 2.8 3.6 SS 3.00 3.60 Min Max 110 1.3 2 ...

Page 148

... ST72651AR6 13.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ADC enabled STAB Conversion time (Sample+Hold Sample capacitor loading time ...

Page 149

... E =Differential Linearity Error: maximum deviation D between actual steps and the ideal one. E =Integral Linearity Error: maximum deviation L between any actual transition and the end point correlation line. V (LSB ) in IDEAL ST72651AR6 3) V =3.3V =8MHz CPU Min Max 2.5 -1.0 1.5 -2 ...

Page 150

... ST72651AR6 14 PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers this device in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. ECOPACK 14.1 PACKAGE MECHANICAL DATA Figure 95. 48-Pin Low profile Quad Flat Package D D1 150/161 tions, grade definitions and product status are available at: www ...

Page 151

... Figure 96. 64-Pin Low profile Quad Flat Package 0.10mm .004 seating plane Dim L1 L Note 1. Values in inches are converted from mm and rounded to 4 decimal digits. K Doc ID 7215 Rev 4 ST72651AR6 1) mm inches Min Typ Max Min Typ A 1.60 A1 0.05 0.15 0.0020 A2 1.35 1.40 1.45 0.0530 0.0550 0.0570 b 0 ...

Page 152

... ST72651AR6 14.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: The maximum power dissipation is obtained from the formula P 1. tion of an application can be defined by the user with the formula: P internal power ( and P ...

Page 153

... Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. This protection is based on read and a write pro- tection of the memory in test modes and IAP. Doc ID 7215 Rev 4 ST72651AR6 PE5PU PEOR.5 PEDDR.5 OPTION 0 ...

Page 154

... ST72651AR6 Erasing the option bytes when the FMP_R option is selected will cause the whole user memory to be erased first, and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.4 on page 20 tails. 0: Read-out protection enabled 1: Read-out protection disabled 15 ...

Page 155

... For production programming of ST7 devices, ST’s third-party tool partners also provide a complete range of gang and automated programming solu- tions, which are ready to integrate into your pro- duction environment. Evaluation board Emulator Doc ID 7215 Rev 4 ST72651AR6 In-circuit debugger/ Dedicated programmer programmer STX-RLINK ST7MDTU5-EPB 155/161 ...

Page 156

... ST72651AR6 15.4 ST7 APPLICATION NOTES Table 42. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI A HIGH PRECISION, LOW COST, SINGLE SUPPLY ADC FOR POSITIVE AND NEGATIVE IN- ...

Page 157

... KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN Doc ID 7215 Rev 4 ST72651AR6 157/161 ...

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... ST72651AR6 Table 42. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- ...

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... ST7 I2C, it may ignore the START condition from the other I2C master. In this case, the ST7 master will receive a NACK from the other device. On reception of the NACK, ST7 can send a re-start and Slave address to re-initiate communication. Doc ID 7215 Rev 4 ST72651AR6 159/161 ...

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... ST72651AR6 17 SUMMARY OF CHANGES Date Revision Added “related documentation” section in specific chapters thoughout document Added a note in in description of OVR and MODF bits in Updated note in AF bit description (SR2 register) in note 2 in Added reference to AN1635 in Watchdog hardware in ICC mode and “Unexpected Reset Fetch” added to Important Notes, section 16 on page for LVD on and off ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 7215 Rev 4 ST72651AR6 161/161 ...

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