ST7LIT10BF1

Manufacturer Part NumberST7LIT10BF1
Description8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
ManufacturerSTMicroelectronics
ST7LIT10BF1 datasheet
 

Specifications of ST7LIT10BF1

Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention20 years at 55˚C.128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention20 years at 55˚C.
Clock SourcesInternal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clockFive Power Saving ModesHalt, Active-Halt, Auto Wake-up from Halt, Wait and Slow
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8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
Memories
– up to 4 Kbytes single voltage extended Flash
(XFlash) Program memory with read-out pro-
tection, In-Circuit Programming and In-Appli-
cation programming (ICP and IAP). 10K write/
erase cycles guaranteed, data retention: 20
years at 55°C.
– 256 bytes RAM
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supervisor (LVD) for
main supply and an auxiliary voltage detector
(AVD) with interrupt capability for implement-
ing safe power-down procedures
– Clock sources: Internal 1% RC oscillator (on
ST7FLITE15B and ST7FLITE19B), crystal/
ceramic resonator or external clock
– Internal 32-MHz input clock for Auto-reload
timer
– Optional x4 or x8 PLL for 4 or 8 MHz internal
clock
– Five Power Saving Modes: Halt, Active-Halt,
Auto Wake-up from Halt, Wait and Slow
I/O Ports
– Up to 17 multifunctional bidirectional I/O lines
– 7 high sink outputs
5 Timers
– Configurable watchdog timer
– Two 8-bit Lite Timers with prescaler,
1 realtime base and 1 input capture
– Two 12-bit Auto-reload Timers with 4 PWM
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
Data EEPROM - bytes
Lite Timer with Wdg, Autoreload
Peripherals
Timer, SPI, 10-bit ADC with Op-Amp
Operating Supply
CPU Frequency
Up to 8Mhz(w/ ext OSC at 16MHz)
Operating Temperature
Packages
SO20 300”, DIP20, SO16 300”, DIP16
June 2008
DATA EEPROM, ADC, 5 TIMERS, SPI
Communication Interface
– SPI synchronous serial interface
Interrupt Management
– 12 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (on 4 vectors)
Analog Comparator
A/D Converter
– 7 input channels
– Fixed gain Op-amp
– 13-bit precision for 0 to 430 mV (@ 5V V
– 10-bit precision for 430 mV to 5V (@ 5V V
Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode de-
– 17 main addressing modes
– 8 x 8 unsigned multiply instructions
Development Tools
– Full hardware/software development package
– DM (Debug Module)
ST7LITE10B
-
Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI,
2.7V to 5.5V
Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz)
-40°C to +85°C / -40°C to +125°C
ST7LITE1xB
DIP20
QFN20
DIP16
outputs, 1 input capture, 4 output compare
and one pulse functions
tection
ST7LITE15B
ST7LITE19B
2K/4K
256 (128)
-
10-bit ADC with Op-Amp, Analog Comparator
SO20 300”, DIP20, SO16 300”, DIP16, QFN20
SO20
SO16
300”
)
DD
)
DD
128
Rev 6
1/159
1

ST7LIT10BF1 Summary of contents

  • Page 1

    MCU WITH SINGLE VOLTAGE FLASH MEMORY, Memories ■ – Kbytes single voltage extended Flash (XFlash) Program memory with read-out pro- tection, In-Circuit Programming and In-Appli- cation programming (ICP and IAP). 10K write/ erase cycles guaranteed, data ...

  • Page 2

    INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    ST7LITE1xB 1 INTRODUCTION The ST7LITE1xB is a member of the ST7 micro- controller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. The ST7LITE1xB features FLASH memory with byte-by-byte In-Circuit Programming (ICP) ...

  • Page 5

    PIN DESCRIPTION Figure 2. 20-Pin SO and DIP Package Pinout COMPIN+/SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 COMPIN-/CLKIN/AIN4/PB4 Figure 3. 20-Pin QFN Package Pinout COMPIN+/SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 COMPIN-/CLKIN/AIN4/PB4 RESET 3 4 ei0 ei3 5 6 ...

  • Page 6

    ST7LITE1xB PIN DESCRIPTION (Cont’d) Figure 4. 16-Pin SO and DIP Package Pinout COMPIN+/SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 COMPIN-/CLKIN/AIN4/PB4 6/159 RESET ei0 ei3 ...

  • Page 7

    PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Type input output supply In/Output level CMOS 0.3V T Output level 20mA high sink (on N-buffer only) Port and control configuration: – Input: ...

  • Page 8

    ST7LITE1xB Pin No. Pin Name PA6 /MCO ICCCLK/BREAK PA5 /ICCDATA ATPWM3 PA4/ATPWM2 PA3/ATPWM1 PA2/ATPWM0 PA1/ATIC PA0/LTIC ...

  • Page 9

    REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 256 bytes of RAM, 128 ...

  • Page 10

    ST7LITE1xB Table 2. Hardware Register Map Address Block Register Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR Port C 0007h PCDDR 0008h LTCSR2 0009h LTARR LITE 000Ah LTCNTR TIMER ...

  • Page 11

    Address Block Register Label 0002Fh FLASH FCSR 00030h EEPROM EECSR 0031h SPIDR 0032h SPI SPICR 0033h SPICSR 0034h ADCCSR 0035h ADC ADCDRH 0036h ADCDRL 0037h ITC EICR 0038h MCC MCCSR 0039h Clock and RCCR 003Ah Reset SICSR PLL clock 003Bh ...

  • Page 12

    ST7LITE1xB 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices ...

  • Page 13

    FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface ICP needs a minimum of 4 and pins to be connected to the programming tool. These pins are: – RESET: device reset – device power supply ground SS ...

  • Page 14

    ST7LITE1xB FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually. 4.5.1 Read out Protection Readout protection, when selected provides a pro- ...

  • Page 15

    DATA EEPROM 5.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 7. EEPROM Block ...

  • Page 16

    ST7LITE1xB DATA EEPROM (Cont’d) 5.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 8 describes these different memory access modes. Read ...

  • Page 17

    DATA EEPROM (Cont’d) 2 Figure 9. Data E PROM Write Operation ⇓ Row / Byte ⇒ ROW DEFINITION Byte 1 Byte 2 Writing data latches E2LAT bit Set by USER application E2PGM bit Note programming cycle is interrupted ...

  • Page 18

    ST7LITE1xB DATA EEPROM (Cont’d) 5.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter ...

  • Page 19

    DATA EEPROM (Cont’d) 5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC- SR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This ...

  • Page 20

    ST7LITE1xB 6 CENTRAL PROCESSING UNIT 6.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing ...

  • Page 21

    CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This ...

  • Page 22

    ST7LITE1xB CPU REGISTERS (Cont’d) STACK POINTER (SP) Read/Write Reset Value: 01FFh SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location ...

  • Page 23

    SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features Clock ...

  • Page 24

    ST7LITE1xB – The x8 PLL is intended for operation with V 1) the 3.3V to 5.5V range Refer to Section 15.1 for the option byte descrip- tion. If the PLL is disabled and the RC oscillator is ena- bled, then ...

  • Page 25

    REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable This bit ...

  • Page 26

    ST7LITE1xB Figure 14. Clock Management Block Diagram 7 CR9 CR8 CR7 1% RC OSC,PLLOFF, CLKSEL[1:0] Option bits CLKIN CLKIN CLKIN CLKIN OSC /OSC1 1-16 MHZ OSC2 f OSC /32 DIVIDER Note: The PLL cannot be used with the external resonator ...

  • Page 27

    MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block (1 to 16MHz): an external source ■ 5 different configurations for crystal or ceramic ■ resonator oscillators ...

  • Page 28

    ST7LITE1xB 7.5 RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ Note: A reset ...

  • Page 29

    Figure 16. Reset Block Diagram V DD RESET Note 1: See “Illegal Opcode Reset” on page 107. for more details on illegal opcode reset conditions Filter PULSE GENERATOR ST7LITE1xB INTERNAL RESET WATCHDOG RESET 1) ILLEGAL OPCODE RESET LVD ...

  • Page 30

    ST7LITE1xB RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 7.5.3 External ...

  • Page 31

    SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions managed by the SICSR register. Note: A reset can also be triggered following the detection ...

  • Page 32

    ST7LITE1xB SYSTEM INTEGRITY MANAGEMENT (Cont’d) Figure 19. Reset and Supply Management Block Diagram RESET SEQUENCE RESET MANAGER (RSM 32/159 1 WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT SICSR WDGRF AUXILIARY VOLTAGE STATUS FLAG AVD ...

  • Page 33

    SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply voltage (V ). The V AVD IT-(AVD) for falling ...

  • Page 34

    ST7LITE1xB SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.3 Low Power Modes Mode Description No effect on SI. AVD interrupts cause the WAIT device to exit from Wait mode. The SICSR register is frozen. HALT The AVD remains active. 7.6.3.1 Interrupts The AVD ...

  • Page 35

    SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0110 0xx0 (6xh) 7 LOCK WDG CR1 CR0 LOCKED LVDRF AVDF AVDIE 32 RF Bit 7 = LOCK32 PLL 32Mhz Locked Flag This bit ...

  • Page 36

    ST7LITE1xB 8 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in ...

  • Page 37

    INTERRUPTS (cont’d) Figure 21. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 5. Interrupt Mapping Source N° Block RESET Reset TRAP Software Interrupt 0 AWU Auto Wake Up Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ...

  • Page 38

    ST7LITE1xB INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 IS21 IS20 IS11 Bits 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Table Bits ...

  • Page 39

    INTERRUPTS (Cont’d) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin selection ei11 ...

  • Page 40

    ST7LITE1xB 9 POWER SAVING MODES 9.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the ST7 (see Figure 22): Slow ■ Wait ...

  • Page 41

    POWER SAVING MODES (Cont’d) 9.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT ...

  • Page 42

    ST7LITE1xB POWER SAVING MODES (Cont’d) 9.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when ACTIVE-HALT is disabled (see section 9.5 on page 43 when the ...

  • Page 43

    POWER SAVING MODES (Cont’d) 9.4.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/ ...

  • Page 44

    ST7LITE1xB POWER SAVING MODES (Cont’d) Figure 27. ACTIVE-HALT Timing Overview ACTIVE 256 OR 4096 CPU RUN HALT CYCLE DELAY RESET OR HALT INTERRUPT INSTRUCTION [Active Halt Enabled] Figure 28. ACTIVE-HALT Mode Flow-chart OSCILLATOR PERIPHERALS HALT INSTRUCTION CPU (Active Halt enabled) ...

  • Page 45

    POWER SAVING MODES (Cont’d) Similarities with Halt mode The following AWUFH mode behaviour is the same as normal Halt mode: – The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a re- ...

  • Page 46

    ST7LITE1xB POWER SAVING MODES (Cont’d) Figure 31. AWUFH Mode Flow-chart HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE 0 1) WDGHALT 1 AWU RC OSC WATCHDOG MAIN OSC RESET PERIPHERALS CPU I[1:0] BITS INTERRUPT AWU RC OSC Y MAIN ...

  • Page 47

    POWER SAVING MODES (Cont’d) 9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h Bits 7:3 = Reserved. Bit 1= AWUF Auto Wake Up Flag This bit is set by hardware ...

  • Page 48

    ST7LITE1xB 10 I/O PORTS 10.1 INTRODUCTION The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may ...

  • Page 49

    RIM instruc- tion (in cases where a pin level change could occur) 10.2.2 Output Modes Setting the DDRx bit selects output mode. Writing to the DR bits applies a ...

  • Page 50

    ST7LITE1xB I/O PORTS (Cont’d) Figure 32. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS From on-chip periphera ALTERNATE ENABLE BIT DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT REQUEST ( ...

  • Page 51

    I/O PORTS (Cont’d) Table 9. I/O Configurations PAD PAD PAD Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output ...

  • Page 52

    ST7LITE1xB I/O PORTS (Cont’d) Analog alternate function Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, ...

  • Page 53

    I/O PORTS (Cont’d) 10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION The I/O port register configurations are summa- rised as follows. Standard Ports PA7:0, PB6:0 MODE floating input pull-up input open drain output push-pull output PC1:0 (multiplexed with OSC1,OSC2) MODE floating input push-pull ...

  • Page 54

    ST7LITE1xB Address Register Label (Hex.) PAOR MSB 0002h Reset Value PBDR MSB 0003h Reset Value PBDDR MSB 0004h Reset Value PBOR MSB 0005h Reset Value PCDR MSB 0006h Reset Value PCDDR MSB 0007h Reset Value 10.8 MULTIPLEXED INPUT/OUTPUT PORTS OSC1/PC0 ...

  • Page 55

    ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...

  • Page 56

    ST7LITE1xB WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is free- running: it counts down even if the watchdog is disabled. The ...

  • Page 57

    DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) 11.2.1 Introduction The 12-bit Autoreload Timer can be used for gen- eral-purpose timing functions based on one or two free-running 12-bit upcounters with an input capture register and four PWM output ...

  • Page 58

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Figure 36. Dual Timer Mode (ENCNTR2=1) ATIC Edge Detection Circuit 12-Bit Autoreload Register 1 12-Bit Upcounter 1 12-Bit Upcounter 2 12-Bit Autoreload Register 2 Clock Control 1 ms from Lite Timer LTIC 58/159 ...

  • Page 59

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3 Functional Description 11.2.3.1 PWM Mode This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins. PWM Frequency The four PWM signals can have the ...

  • Page 60

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Figure 38. PWM Function 4095 DUTY CYCLE REGISTER (DCRx) AUTO-RELOAD REGISTER (ATR) 000 WITH OE=1 AND OPx=0 WITH OE=1 AND OPx=1 Figure 39. PWM Signal from 0% to 100% Duty Cycle f COUNTER ...

  • Page 61

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.2 Dead Time Generation A dead time can be inserted between PWM0 and PWM1 using the DTGR register. This is required for half-bridge driving where PWM signals must not be overlapped. The non-overlapping PWM0/ ...

  • Page 62

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.3 Break Function The break function can be used to perform an emergency shutdown of the application being driv the PWM signals. The break function is activated by the external BREAK ...

  • Page 63

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.4 Output Compare Mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and DCRxL ...

  • Page 64

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.5 Input Capture Mode The 12-bit ATICR register is used to latch the val the 12-bit free running upcounter CNTR1 af- ter a rising or falling edge is detected on the ...

  • Page 65

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Long Input Capture ■ Pulses that last more than 8μs can be measured with an accuracy of 4μ OSC lowing conditions: – The 12-bit AT4 Timer is clocked by the Lite Timer ...

  • Page 66

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) – At the second input capture on the falling edge of the pulse, we assume that the values in the reg- isters are as follows: LTICR = LT2 ATICRH = ATH2 ATICRL = ...

  • Page 67

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.6 One Pulse Mode One Pulse Mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in dual timer mode i.e. only for CNTR2, when the ...

  • Page 68

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 8. Set the OP_EN bit in the PWM3CSR register to enable one-pulse mode. 9. Enable the PWM3 output by setting the OE3 bit in the PWMCR register. The "Wait for Overflow event" in ...

  • Page 69

    Figure 49. Dynamic DCR2/3 update in One Pulse Mode f counter2 000 CNTR2 LTIC FORCE2 TRAN2 DCR2/3 (DCR2/3) old PWM2/3 (DCR3) FFF 000 old (DCR2/3) extra PWM3 period due to DCR3 update dynamically in one-pulse mode. ST7LITE1xB (DCR3) ATR2 000 ...

  • Page 70

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.3.7 Force Update In order not to wait for the counter load the value into active DCRx registers, a pro- grammable counter overflow is provided. For x both counters, a separate bit is ...

  • Page 71

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.4 Low Power Modes Mode Description WAIT No effect on AT timer HALT AT timer halted. 11.2.5 Interrupts Enable Interrupt Event Control Event Flag Bit Overflow OVF1 OVIE1 Event AT4 IC Event ICF ICIE ...

  • Page 72

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h ICF ICIE CK1 CK0 Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. ...

  • Page 73

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) AUTORELOAD REGISTER (ATR1H) Read / Write Reset Value: 0000 0000 (00h ATR11 ATR10 ATR9 AUTORELOAD REGISTER (ATR1L) Read / Write Reset Value: 0000 0000 (00h) 7 ATR7 ATR6 ATR5 ...

  • Page 74

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h) 7 BRSEL BREDGE BA BPEN PWM3 PWM2 PWM1 PWM0 Bit 7 = BRSEL Break Input Selection This bit is read/write by software and ...

  • Page 75

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. The ATICR register contains captured the value of the ...

  • Page 76

    ST7LITE1xB DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Bit 1= TRAN2 Transfer enable2 This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows ...

  • Page 77

    DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Table 14. Register Map and Reset Values Address Register 7 Label (Hex.) ATCSR 0D 0 Reset Value CNTR1H 0E 0 Reset Value CNTR1L CNTR1_7 0F Reset Value 0 ATR1H 10 0 Reset Value ATR1L ...

  • Page 78

    ST7LITE1xB Address Register 7 Label (Hex.) FORCE2 ATCSR2 21 Reset Value 0 BRSEL BREAKCR 22 Reset Value 0 ATR2H 23 0 Reset Value ATR2L ATR7 24 Reset Value 0 DTE DTGR 25 Reset Value 0 BREAKEN 26 0 Reset Value ...

  • Page 79

    LITE TIMER 2 (LT2) 11.3.1 Introduction The Lite Timer can be used for general-purpose timing functions based on two free-running 8- bit upcounters and an 8-bit input capture register. 11.3.2 Main Features Realtime Clock ■ – One ...

  • Page 80

    ST7LITE1xB LITE TIMER (Cont’d) 11.3.3 Functional Description 11.3.3.1 Timebase Counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f overflow event ...

  • Page 81

    LITE TIMER (Cont’d) 11.3.4 Low Power Modes Mode Description No effect on Lite timer SLOW (this peripheral is driven directly by f /32) OSC WAIT No effect on Lite timer ACTIVE HALT No effect on Lite timer HALT Lite timer ...

  • Page 82

    ST7LITE1xB LITE TIMER (Cont’d) Bit 6 = ICF Input Capture Flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value input capture ...

  • Page 83

    LITE TIMER (Cont’d) Table 15. Lite Timer Register Map and Reset Values Address Register Label (Hex.) LTCSR2 08 Reset Value LTARR AR7 09 Reset Value LTCNTR CNT7 0A Reset Value LTCSR1 ICIE 0B Reset Value LTICR ICR7 0C Reset Value ...

  • Page 84

    ST7LITE1xB ON-CHIP PERIPHERALS (cont’d) 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a ...

  • Page 85

    SERIAL PERIPHERAL INTERFACE (SPI) (cont’d) Figure 53. Serial Peripheral Interface Block Diagram SPIDR MOSI MISO 8-bit Shift Register SOD bit SCK SS Data/Address Bus Read Read Buffer Write MASTER CONTROL SERIAL CLOCK GENERATOR Interrupt request 7 SPIF WCOL OVR MODF ...

  • Page 86

    ST7LITE1xB SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 2. The MOSI pins are connected together and the MISO pins are connected together. In ...

  • Page 87

    SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...

  • Page 88

    ST7LITE1xB SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: ...

  • Page 89

    SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 5). Note: The idle state of SCK must correspond to the polarity selected ...

  • Page 90

    ST7LITE1xB SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.5 Error Flags 11.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master de- vice’s SS pin is pulled low. When a Master mode fault occurs: – The MODF bit is set and ...

  • Page 91

    SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured using a device as the master and ...

  • Page 92

    ST7LITE1xB SERIAL PERIPHERAL INTERFACE (cont’d) 11.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ...

  • Page 93

    Register Description SPI CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 Bit 7 = SPIE Serial Peripheral Interrupt Enable This bit is set and cleared by software. 0: Interrupt is ...

  • Page 94

    ST7LITE1xB SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF - Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only) This bit is set ...

  • Page 95

    SERIAL PERIPHERAL INTERFACE (Cont’d) Table 17. SPI Register Map and Reset Values Address Register Label (Hex.) SPIDR MSB 0031h Reset Value SPICR SPIE 0032h Reset Value SPICSR SPIF 0033h Reset Value SPE SPR2 MSTR ...

  • Page 96

    ST7LITE1xB 11.5 10-BIT A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels ...

  • Page 97

    A/D CONVERTER (ADC) (Cont’d) 11.5.3.2 Input Voltage Amplifier The input voltage can be amplified by a factor enabling the AMPSEL bit in the ADCDRL regis- ter. When the amplifier is enabled, the input range is 0V ...

  • Page 98

    ST7LITE1xB 10-BIT A/D CONVERTER (ADC) (Cont’d) 11.5.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 0 Bit 7 = EOC End of Conversion This bit is set ...

  • Page 99

    A/D CONVERTER (ADC) (Cont’d) Bit 2 = AMPSEL Amplifier Selection Bit This bit is set and cleared by software. 0: Amplifier is not selected 1: Amplifier is selected Note: When AMPSEL mandatory that f be less than ...

  • Page 100

    ST7LITE1xB 11.6 ANALOG COMPARATOR (CMP) 11.6.1 Introduction The CMP block consists of an analog comparator and an internal voltage reference. The voltage ref- erence can be external or internal, selectable un- der program control. The comparator input pins COMPIN+ and ...

  • Page 101

    ANALOG COMPARATOR (Cont’d) Figure 61. Analog Comparator and Internal Voltage Reference COMPIN+ (PB0) 1.2V Bandgap COMPIN- (PB4) Figure 62. Analog Comparator Comparator + - Rising Edge Falling Edge CHYST CMPCR ADC channel 0 Voltage Reference 4 VR[3:0] bits VCBGR bit ...

  • Page 102

    ST7LITE1xB ANALOG COMPARATOR (Cont’d) 11.6.4 Register Description Internal Voltage Reference Register (VREFCR) Read/Write Reset Value : 0000 0000 (00h) 7 VCEXT VCBGR VR3 VR2 VR1 Bit 7 = VCEXT External Voltage Reference for Comparator This bit is set or cleared ...

  • Page 103

    ANALOG COMPARATOR (Cont’d) Bit 4 = CMPIF Comparator Interrupt Flag This bit is set by hardware when interrupt is gener- ated at the rising edge (CINV = 0) or falling edge (CINV = 1) of comparator output. This bit is ...

  • Page 104

    ST7LITE1xB 12 INSTRUCTION SET 12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in seven main groups: Addressing Mode Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...

  • Page 105

    ST7 ADDRESSING MODES (cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...

  • Page 106

    ST7LITE1xB ST7 ADDRESSING MODES (cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index ...

  • Page 107

    INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and ...

  • Page 108

    ST7LITE1xB INSTRUCTION GROUPS (cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) ...

  • Page 109

    INSTRUCTION GROUPS (cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...

  • Page 110

    ST7LITE1xB 13 ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 13.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions ...

  • Page 111

    ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 13.2.1 Voltage Characteristics Symbol ...

  • Page 112

    ST7LITE1xB 13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions: Suffix 6 Devices T = -40 to +85°C unless otherwise specified. A Symbol Parameter V Supply voltage DD f CPU clock frequency CPU 13.3.2 General Operating Conditions: Suffix 3 Devices T = ...

  • Page 113

    Operating Conditions with Low Voltage Detector (LVD) 13.3.3.1 Operating Conditions with LVD at T Symbol Parameter Reset release threshold V (LVD) IT+ (V rise) DD Reset generation threshold V (LVD) IT- (V fall LVD voltage threshold hysteresis ...

  • Page 114

    ST7LITE1xB 13.3.4 Auxiliary Voltage Detector (AVD) Thresholds T = -40 to 125°C, unless otherwise specified A Symbol Parameter 1=>0 AVDF flag toggle threshold V (AVD) IT+ (V rise) DD 0=>1 AVDF flag toggle threshold V (AVD) IT- (V fall) DD ...

  • Page 115

    OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. 13.3.5.1 Devices with ‘”6” or “3”order code suffix (tested for T Symbol Parameter Internal RC oscillator fre quency Accuracy of ...

  • Page 116

    ST7LITE1xB Figure 66. Typical accuracy with RCCR=RCCR0 vs V 3.50% 3.00% 2.50% 2.00% 1.50% 1.00% 0.50% 0.00% -0.50% -1.00% 4.5 Figure 67. Typical RCCR0 vs V 1.025 1.02 1.015 1.01 1.005 1 0.995 0.99 0.985 0.98 4.5 4.6 116/159 DD ...

  • Page 117

    OPERATING CONDITIONS (Cont’d) 13.3.5.2 Devices with ‘”6” or “3” order code suffix (tested for T Symbol Parameter Internal RC oscillator fre quency Accuracy of Internal RC ACC oscillator when calibrated RC with RCCR=RCCR1 RC oscillator current con- ...

  • Page 118

    ST7LITE1xB OPERATING CONDITIONS (Cont’d) Figure 68. Typical accuracy with RCCR=RCCR1 vs V 1.50% 1.00% 0.50% 0.00% -0.50% -1.00% Figure 69. Typical RCCR1 vs V 1.01 1.005 1 0.995 0.99 0.985 0.98 3 118/159 DD 3 3.1 3.2 3.3 Vdd (V) ...

  • Page 119

    OPERATING CONDITIONS (Cont’d) Figure 70. PLL Δf /f versus time CPU CPU Δf /f CPU CPU Max 0 Min 13.3.5.3 32MHz PLL T = -40 to 125°C, unless otherwise specified A Symbol V Voltage DD f Frequency PLL32 f Input ...

  • Page 120

    ST7LITE1xB 13.3.6 Operating conditions with ADC T = -40 to 125°C, unless otherwise specified A Symbol 1) I Injected current on any analog pin INJ(ANA) Note: 1. Current injection (negative or positive) not allowed on any analog pin. 120/159 Parameter ...

  • Page 121

    SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- 13.4.1 Supply Current T = -40 ...

  • Page 122

    ST7LITE1xB Figure 73. Typical I in SLOW vs 0.90 0.80 250KHz 0.70 125KHz 0.60 62KHz 0.50 0.40 0.30 0.20 0.10 0.00 2.7 3.3 VDD (V) Note: Graph displays data beyond the normal operating range 5.5V ...

  • Page 123

    On-chip peripherals Symbol I 12-bit Auto-Reload Timer supply current DD(AT) I SPI supply current DD(SPI) I ADC supply current when converting DD(ADC) Notes: 1. Data based on a differential I DD mode at f =8MHz. cpu 2. Data based ...

  • Page 124

    ST7LITE1xB 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 13.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT v(IT) c(INST) Notes: 1. Guaranteed by Design. ...

  • Page 125

    CLOCK AND TIMING CHARACTERISTICS (Cont’d) 13.5.4 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with ten different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external ...

  • Page 126

    ST7LITE1xB 13.6 MEMORY CHARACTERISTICS T = -40°C to 125°C, unless otherwise specified A 13.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 13.6.2 FLASH Program Memory Symbol Parameter V Operating voltage for Flash write/erase DD Programming time ...

  • Page 127

    EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed ...

  • Page 128

    ST7LITE1xB EMC CHARACTERISTICS (Cont’d) 13.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, ...

  • Page 129

    I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V 1) hys hysteresis I Input leakage current ...

  • Page 130

    ST7LITE1xB I/O PORT PIN CHARACTERISTICS (Cont’d) 13.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 83) 1) ...

  • Page 131

    I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 81. Typical 140°C 0.9 90°C 0.8 25°C 0.7 0.6 -5°C 0.5 -45°C 0.4 0.3 0.2 0 0.5 1 1.5 Iol (mA) Figure 82. Typical ...

  • Page 132

    ST7LITE1xB I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 87. Typical 0.8 140°C 0.7 90°C 0.6 25°C 0.5 -5°C 0.4 -45°C 0.3 0.2 0 Iol (mA) Figure 88. Typical ...

  • Page 133

    I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 93. Typical 1.2 140°C 1 90°C 25°C 0.8 -5°C 0.6 -45°C 0.4 0 0.5 1 1.5 Iol (mA) Figure 94. Typical 0.9 140°C 0.8 ...

  • Page 134

    ST7LITE1xB I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 99. Typical 0.8 140°C 0.7 90°C 0.6 25°C 0.5 -5°C 0.4 -45°C 0.3 0.2 0 0.5 1 1.5 Iol (mA) Figure 100. Typical ...

  • Page 135

    CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin T = -40°C to 125°C, unless otherwise specified A Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys V Output low ...

  • Page 136

    ST7LITE1xB CONTROL PIN CHARACTERISTICS (Cont’d) Figure 105. RESET pin protection when LVD is enabled. Required EXTERNAL RESET 0.01μF Figure 106. RESET pin protection when LVD is disabled. USER EXTERNAL RESET CIRCUIT 0.01μF Required Note 1: – The reset network protects ...

  • Page 137

    COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise ...

  • Page 138

    ST7LITE1xB COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 108. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t MOSI INPUT Figure 109. SPI Master ...

  • Page 139

    ADC CHARACTERISTICS Subject to general operating condition for V Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ADC ...

  • Page 140

    ST7LITE1xB ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V =5.0V DD Symbol Parameter E Total unadjusted error T E Offset error O E Gain Error G E Differential linearity error D E Integral linearity error L Notes: 1. Data based on ...

  • Page 141

    ADC CHARACTERISTICS (Cont’d) Figure 112. ADC Accuracy Characteristics with amplifier enabled Digital Result ADCDR 704 V V – DD 1LSB = ------------------------------- - IDEAL 1024 LSB 108 62.5mV Note: ...

  • Page 142

    ST7LITE1xB ADC CHARACTERISTICS (Cont’d) Symbol Parameter V Amplifier operating voltage DD(AMP) V Amplifier input voltage Amplifier output offset voltage OFFSET 1) V Step size for monotonicity STEP 1) Output Voltage Response Linearity 1) Gain factor Amplified Analog ...

  • Page 143

    ANALOG COMPARATOR CHARACTERISTICS Symbol Parameter V Supply range DDA V Comparator input voltage range IN Temp Temperature range V Comparator offset error offset Analog Comparator Consumption I Analog Comparator Consumption DD(CMP) during power-down t Comparator propagation delay propag t ...

  • Page 144

    ST7LITE1xB 14 PACKAGE CHARACTERISTICS In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level in- terconnect. The category of second Level Inter- connect is marked on the package and on ...

  • Page 145

    PACKAGE CHARACTERISTICS (Cont’d) Figure 114. 16-Pin Plastic Small Outline Package, 300-mil Width Figure 115. 20-Pin Plastic Dual In-Line Package, 300-mil Width ...

  • Page 146

    ST7LITE1xB PACKAGE CHARACTERISTICS (Cont’d) Figure 116. 20-Pin Plastic Small Outline Package, 300-mil Width Figure 117. 20-Lead Very thin Fine pitch Quad Flat No-Lead Package 146/159 h x 45× Dim. Min ...

  • Page 147

    Table 24. THERMAL CHARACTERISTICS Symbol Ratings Package thermal resistance R thJA (junction to ambient) T Maximum junction temperature Jmax P Power dissipation Dmax Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is ...

  • Page 148

    ... ST7LITE1xB 14.2 SOLDERING INFORMATION In accordance with the RoHS European directive, all STMicroelectronics packages have been con- verted to lead-free technology, named ECO- TM PACK . TM ECOPACK packages are qualified according ■ to the JEDEC STD-020C compliant soldering profile. Detailed information on the STMicroelectronics ■ TM ECOPACK transition program is available on www ...

  • Page 149

    DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (FLASH). 15.1 OPTION BYTES The two option bytes allow the hardware configu- ration of the microcontroller to be selected. The option bytes can ...

  • Page 150

    ST7LITE1xB OPTION BYTES (Cont’d) OPTION BYTE 1 OPT7 = PLLx4x8 PLL Factor selection. 0: PLLx4 1: PLLx8 OPT6 = PLLOFF PLL disable. 0: PLL enabled 1: PLL disabled (by-passed) OPT5 = PLL32OFF 32MHz PLL disable. 0: PLL32 enabled 1: PLL32 ...

  • Page 151

    DEVICE ORDERING INFORMATION Figure 118. Ordering information scheme Example: Family ST7 Microcontroller Family Memory type F: Flash P: FASTROM Version 10B, 15B or 19B No. of pins Memory size ...

  • Page 152

    ... Reference/FASTROM Code *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. ...

  • Page 153

    ... DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers in- clude a complete range of hardware systems and software tools from STMicroelectronics and third- party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. ...

  • Page 154

    ST7LITE1xB 15.4 ST7 APPLICATION NOTES Table 29. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION ...

  • Page 155

    Table 29. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK ...

  • Page 156

    ST7LITE1xB Table 29. ST7 Application Notes IDENTIFICATION DESCRIPTION AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ...

  • Page 157

    REVISION HISTORY Date Revision 20-Dec-05 1 Initial release on internet Added reset default state in bold for RESET, PC0 and PC1 in tion,” on page 7 Changed note below DLING” on page 18 Modified note and ...

  • Page 158

    ST7LITE1xB Date Revision Added QFN20 pinout with new mechanical data page 27-Nov-06 4 Added ST7FLI19BY1M3TR sales type in Modifed “DEVELOPMENT TOOLS” on page 153 Added note 1 to Table 1 on page 7 Modified note 1 in Added caution to ...

  • Page 159

    ... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...