ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 102

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ST7LIT10BF1

Manufacturer Part Number
ST7LIT10BF1
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LIT10BF1

Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
Clock Sources
Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow
ST7LITE1xB
ANALOG COMPARATOR (Cont’d)
11.6.4 Register Description
Internal Voltage Reference Register (VREFCR)
Read/Write
Reset Value : 0000 0000 (00h)
Bit 7 = VCEXT External Voltage Reference for
Comparator
This bit is set or cleared by software. It is used to
connect the external reference voltage to the VN
comparator input.
0: External reference voltage not connected to VN
1: External reference voltage connected to VN
Bit 6 = VCBGR Bandgap Voltage for Comparator
This bit is set or cleared by software. It is used to
connect the bandgap voltage of 1.2V to the VN
comparator input.
0: Bandgap voltage not connected to VN
1: Bandgap voltage connected to VN
Bits 5:2 = VR[3:0] Programmable Internal Voltage
Reference Range Selection
These bits are set or cleared by software. They are
used to select one of 16 different voltages availa-
ble from the internal voltage reference module and
connect it to comparator input VN.
Refer to
Table 20. Voltage Reference Programming
102/159
VCEXT VCBGR VR3
VCEXT
bit
7
1
0
0
0
0
0
0
0
0
0
0
0
VCBGR
Table
bit
x
1
0
0
0
0
0
0
0
0
0
0
20.
VR3
bit
1
1
1
1
1
1
1
1
0
0
x
x
VR2
VR2
bit
1
1
1
1
0
0
0
0
1
1
x
x
VR1
bit
x
x
1
1
0
0
1
1
0
0
1
1
VR1
VR0
bit
x
x
1
0
1
0
1
0
1
0
1
0
VR0
VN Voltage
1.2 bandgap
VEXT
3.2V
2.8V
2.6V
2.4V
2.2V
1.8V
1.6V
1.4V
0
3V
2V
0
0
Bits 1:0 = Reserved, Must be kept cleared.
Comparator Control Register (CMPCR)
Read/Write
Reset Value : 1000 0000 (80h)
Bit 7= CHYST Comparator Hysteresis Enable
This bit is set or cleared by software and set by
hardware reset. When this bit is set, the compara-
tor hysteresis is enabled.
0: Hysteresis disabled
1: Hysteresis enabled
Note: To avoid spurious toggling of the output of
the comparator due to noise on the voltage refer-
ence, it is recommended to enable the hysteresis.
Bit 6 = Reserved, Must be kept cleared
Bit 5 = CINV Comparator Output Inversion Select
This bit is set or cleared by software and cleared
by hardware reset. When this bit is set, the compa-
rator output is inverted.
If interrupt enable bit CMPIE is set in the CMPCR
register, the CINV bit is also used to select which
type of level transition on the comparator output
will generate the interrupt. When this bit is reset,
interrupt will be generated at the rising edge of the
comparator output change (COMP signal, refer to
Figure 62 on page
rupt will be generated at the falling edge of compa-
rator output change (COMP signal, refer to
62 on page
0: Comparator output not inverted and interrupt
1: Comparator output inverted and interrupt gener-
VCEXT
CHY-
ST
7
generated at the rising edge of COMP
ated at the falling edge of COMP
bit
0
0
0
0
0
0
0
VCBGR
bit
0
0
0
0
0
0
CINV CMPIF CMPIE CMP
101).
VR3
bit
0
0
0
0
0
0
101). When this bit is set, inter-
VR2
bit
1
1
0
0
0
0
VR1
bit
0
0
1
1
0
0
VR0
bit
1
0
1
0
1
0
COUT CMPON
VN Voltage
1.2V
0.8V
0.6V
0.4V
0.2V
1V
Figure
0

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