ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 107

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
The whole instruction becomes:
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Load and Transfer
Stack operation
Increment/Decrement
Compare and Tests
Logical operations
Bit Operation
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
Unconditional Jump or Call
Conditional Branch
Interruption management
Condition Code Flag modification
PC-2 End of previous instruction
PC-1 Prebyte
PC
PC+1 Additional word (0 to 2) according to the
Opcode
number of bytes required to compute the
effective address
LD
PUSH
INC
CP
AND
BSET
BTJT
ADC
SLL
JRA
JRxx
TRAP
SIM
CLR
POP
DEC
TNZ
OR
BRES
BTJF
ADD
SRL
JRT
WFI
RIM
be subdivided into 13 main groups as illustrated in
the following table:
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
PDY 90 Replace an X based instruction using
PIX 92 Replace an instruction using direct, di-
PIY 91 Replace an instruction using X indirect
RSP
BCP
XOR
SUB
SRA
JRF
HALT
SCF
CPL
SBC
RLC
JP
IRET
RCF
immediate, direct, indexed, or inherent
addressing mode by a Y one.
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
indexed addressing mode by a Y one.
NEG
MUL
RRC
CALL
SWAP
CALLR
ST7LITE1xB
SLA
NOP
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RET