ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 124

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

ST7LITE1xB
13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V
13.5.1 General Timings
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Δt
ish the current instruction execution.
4. Data based on design simulation and/or technology characteristics, not tested in production.
13.5.2 External Clock Source
Figure 78. Typical Application with an External Clock Source
13.5.3 Auto Wakeup from Halt Oscillator (AWU)
Note: 1. Guaranteed by Design. Not tested in production.
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t
t
w(OSC1H) or
f
t
V
w(OSC1L) or
V
AWU
RCSRT
Symbol
t
t
Symbol
t
V
V
OSC1H
OSC1L
r(OSC1) or
f(OSC1) or
c(INST)
t
OSC1H
OSC1L
v(IT)
Symbol
or V
or V
or V
or V
I
L
t
t
t
t
CLKINL
w(CLKINH)
w(CLKINL)
r(CLKIN)
f(CLKIN)
CLKINH
Instruction cycle time
Interrupt reaction time
t
CLKIN_H
CLKIN_L
v(IT)
AWU Oscillator Frequency
AWU Oscillator startup time
EXTERNAL
CLOCK SOURCE
= Δt
c(INST)
Parameter
OSC1/CLKIN input pin high level voltage
OSC1/CLKIN input pin low level voltage
OSC1/CLKIN high or low time
OSC1/CLKIN rise or fall time
OSCx/CLKIN Input leakage current
t
Parameter
r(OSC1 or CLKIN))
+ 10
1)
1)
3)
Parameter
t
f(OSC1 or CLKIN)
OSC2
OSC1/CLKIN
90%
f
f
DD
CPU
CPU
4)
10%
, f
4)
=8MHz
=8MHz
OSC
Conditions
Conditions
t
, and T
w(OSC1H or CLKINH))
Not connected internally
see
V
A
SS
Conditions
.
c(INST)
≤V
Figure 78
IN
≤V
I
L
is the number of t
DD
t
w(OSC1L or CLKINL)
1.25
Min
250
10
2
Min
50
f
0.7xV
OSC
Min
V
15
Typ
ST72XXX
SS
375
Typ
125
DD
3
CPU
2)
Typ
cycles needed to fin-
1500
Max
2.75
Max
250
12
22
50
0.3xV
Max
V
15
±1
DD
DD
Unit
Unit
kHz
t
t
CPU
CPU
μs
µs
ns
Unit
μA
ns
V