ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 35

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

SYSTEM INTEGRITY MANAGEMENT (Cont’d)
7.6.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read/Write
Reset Value: 0110 0xx0 (6xh)
Bit 7 = LOCK32 PLL 32Mhz Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL 32Mhz reaches its oper-
ating frequency
0: PLL32 not locked
1: PLL32 locked
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-
justment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain an
accuracy of 1%. Refer to
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(reading the SICSR register or writing 0 to this bit)
or by an LVD Reset (to ensure a stable cleared
state of the WDGRF flag when the CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
LOCK
32
7
CR1 CR0
External RESET pin
RESET Sources
Watchdog
LVD
WDG
RF
LOCKED LVDRF AVDF AVDIE
section 7.3 on page
LVDRF
0
0
1
WDGRF
X
0
1
25.
0
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 1 = AVDF Voltage Detector Flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen-
erated when the AVDF bit is set. Refer to
20
0: V
1: V
Bit 0 = AVDIE Voltage Detector Interrupt Enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag is
set. The pending interrupt information is automati-
cally cleared when software enters the AVD inter-
rupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
PLL TEST REGISTER (PLLTST)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 : PLLdiv2 PLL clock divide by 2
This bit is read or write by software and cleared by
hardware after reset. This bit will divide the PLL
output clock by 2.
0 : PLL output clock
1 : Divide by 2 of PLL output clock
Refer “Clock Management Block Diagram” on
page 26
Note : Write of this bit will be effective after 2 Tcpu
cycles (if system clock is 8mhz) else 1 cycle (if
system clock is 4mhz) i.e. effective time is 250ns.
Bit 6:0 : Reserved , Must always be cleared
PLLdiv2
and to
7
DD
DD
over AVD threshold
under AVD threshold
Section 7.6.2.1
0
0
0
for additional details.
0
0
ST7LITE1xB
0
Figure
35/159
0
0
1