ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 52

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ST7LIT10BF1

Manufacturer Part Number
ST7LIT10BF1
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LIT10BF1

Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
Clock Sources
Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow
ST7LITE1xB
I/O PORTS (Cont’d)
Analog alternate function
Configure the I/O as floating input to use an ADC
input. The analog multiplexer (controlled by the
ADC registers) switches the analog voltage
present on the selected pin to the common analog
rail, connected to the ADC input.
Analog Recommendations
Do not change the voltage level or loading on any
I/O while conversion is in progress. Do not have
clocking pins located close to a selected analog
pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific I/O port features such as ADC input or
open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in
are potentially risky and should be avoided, since
they may present unwanted side-effects such as
spurious interrupt generation.
Figure 33. Interrupt I/O Port State Transitions
52/159
1
floating/pull-up
interrupt
INPUT
01
(reset state)
floating
INPUT
00
Figure
open-drain
OUTPUT
33. Other transitions
10
XX
= DDR, OR
OUTPUT
push-pull
11
10.4 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to
10.5 LOW POWER MODES
10.6 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and if the I bit in the CC
register is cleared (RIM instruction).
Related Documentation
AN 970: SPI Communication between ST7 and
EEPROM
AN1045: S/W implementation of I2C bus master
AN1048: Software LCD driver
WAIT
HALT
External interrupt on
selected external
event
Mode
Interrupt Event
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
Section
Event
Flag
-
Description
Control
Enable
DDRx
13.8.
ORx
Bit
from
Wait
Exit
Yes
from
Exit
Halt
Yes

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