ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 56

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

ST7LITE1xB
WATCHDOG TIMER (Cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see
.Watchdog
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T[5:0] bits contain the number of increments
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 12.Watchdog Timing
Notes:
1. The timing variation shown in
the unknown status of the prescaler when writing
to the CR register.
2. The number of CPU clock cycles applied during
the RESET phase (256 or 4096) must be taken
into account in addition to these timings.
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
Table 13. Watchdog Timer Register Map and Reset Values
56/159
1
diate reset
which represents the time delay before the
watchdog produces a reset.
Address
Counter Code
002Eh
(Hex.)
WDG
C0h
FFh
Timing):
WDGCR
Reset Value
Register
Label
f
CPU
[ms]
= 8MHz
min
127
1
WDGA
7
0
Table 12
T6
6
1
[ms]
max
128
Table 12
2
is due to
T5
5
1
Refer to the Option Byte description in
on page
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT option)
If Halt mode with Watchdog is enabled by option
byte (No watchdog reset on HALT instruction), it is
recommended before executing the HALT instruc-
tion to refresh the WDG counter, to avoid an unex-
pected WDG reset immediately after waking up
the microcontroller. Same behaviour in active-halt
mode.
11.1.5 Interrupts
None.
11.1.6 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
WDGA
7
T4
4
1
149.
T6
T3
3
1
T5
T4
T2
2
1
T3
T2
T1
1
1
section 15
T1
T0
0
1
T0
0