ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 61

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.2 Dead Time Generation
A dead time can be inserted between PWM0 and
PWM1 using the DTGR register. This is required
for half-bridge driving where PWM signals must
not be overlapped. The non-overlapping PWM0/
PWM1 signals are generated through a program-
mable dead time by setting the DTE bit.
Dead time value = DT[6:0] x Tcounter1
DTGR[7:0] is buffered inside so as to avoid de-
forming the current PWM cycle. The DTGR effect
will take place only after an overflow.
Figure 40. Dead Time Generation
In the above example, when the DTE bit is set:
– PWM goes low at DCR0 match and goes high at
– PWM1 goes high at DCR0+Tdt and goes low at
ATR1+Tdt
ATR match.
CK_CNTR1
CNTR1
PWM 1
PWM 0
PWM 0
PWM 1
counter = DCR0
DCR0
DCR0+1
T
counter1
T
dt
counter = DCR1
OVF
Notes:
1. Dead time is generated only when DTE=1 and
DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM out-
put signals will be at their reset state.
2. Half Bridge driving is possible only if polarities of
PWM0 and PWM1 are not inverted, i.e. if OP0 and
OP1 are not set. If polarity is inverted, overlapping
PWM0/PWM1 signals will be generated.
3. Dead Time generation does not work at 1 ms
timebase.
With this programmable delay (Tdt), the PWM0
and PWM1 signals which are generated are not
overlapped.
T
dt
= DT[6:0] x T
ATR1
counter1
T
dt
ST7LITE1xB
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