ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 68

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ST7LIT10BF1

Manufacturer Part Number
ST7LIT10BF1
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LIT10BF1

Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55˚C.
Clock Sources
Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow
ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
8. Set the OP_EN bit in the PWM3CSR register to
enable one-pulse mode.
9. Enable the PWM3 output by setting the OE3 bit
in the PWMCR register.
The "Wait for Overflow event" in step 6 can be re-
placed by forced update (writing the FORCE2 bit).
Figure 47. Block Diagram of One Pulse Mode
Figure 48. One Pulse Mode and PWM Timing Diagram
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1
LTIC pin
Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.
PWM3CSR Register
f
f
counter2
counter2
CNTR2
LTIC
CNTR2
LTIC
PWM2/3
PWM2/3
Edge
Selection
OPEDGE
OVF
ATR2
000
OP_EN
DCR2/3
DCR2/3
12-bit AutoReload Register 2
12-bit Active DCR2/3
OVF
Follow the same procedure for PWM2 with the bits
corresponding to PWM2.
Note: When break is applied in one-pulse mode,
the CNTR2, DCR2/3 & ATR2 registers are reset.
Consequently, these registers have to be initial-
ized again when break is removed.
12-bit Upcounter 2
ATR2
000
OP2/3
DCR2/3
DCR2/3
Generation
PWM
OVF
ATR2
ATR2
PWM2/3
000

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